M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

kasli_sawgmaster: initialize SAWG phase according to RTIO TSC

This commit is contained in:
Sebastien Bourdeauducq 2019-01-27 09:49:31 +08:00
parent 9966e789fc
commit d1ef036948
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py
View File

@ -51,6 +51,7 @@ class SinesUrukulSayma(EnvExperiment):
delay(1*ms) delay(1*ms)
sawg.amplitude1.set(.4) sawg.amplitude1.set(.4)
sawg.frequency0.set_mu(sawg_ftw) sawg.frequency0.set_mu(sawg_ftw)
sawg.phase0.set_mu(sawg_ftw*now_mu() >> 17)
while self.drtio_is_up(): while self.drtio_is_up():
pass pass