From d1ef0369486e025938e3e47273769aefabf570f6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 27 Jan 2019 09:49:31 +0800 Subject: [PATCH] kasli_sawgmaster: initialize SAWG phase according to RTIO TSC --- artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py | 1 + 1 file changed, 1 insertion(+) diff --git a/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py b/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py index 9732b8295..755235905 100644 --- a/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py +++ b/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py @@ -51,6 +51,7 @@ class SinesUrukulSayma(EnvExperiment): delay(1*ms) sawg.amplitude1.set(.4) sawg.frequency0.set_mu(sawg_ftw) + sawg.phase0.set_mu(sawg_ftw*now_mu() >> 17) while self.drtio_is_up(): pass