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artiq
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update NAC3

This commit is contained in:
Sebastien Bourdeauducq 2022-03-29 08:49:43 +08:00
parent 69cda517f6
commit b1cfd343eb
5 changed files with 12 additions and 12 deletions
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4
artiq/coredevice/ad53xx.py
View File

@ -381,8 +381,8 @@ class AD53xx:
gain_err = voltage_to_mu(vfs, self.offset_dacs, self.vref) - ( gain_err = voltage_to_mu(vfs, self.offset_dacs, self.vref) - (
offset_err + 0xffff) offset_err + 0xffff)
# NAC3TODO assert offset_err <= 0 assert offset_err <= 0
# NAC3TODO assert gain_err >= 0 assert gain_err >= 0
self.core.break_realtime() self.core.break_realtime()
self.write_offset_mu(channel, 0x8000-offset_err) self.write_offset_mu(channel, 0x8000-offset_err)

8
artiq/coredevice/ad9912.py
View File

@ -62,8 +62,8 @@ class AD9912:
:param data: Data to be written: int32 :param data: Data to be written: int32
:param length: Length in bytes (1-4) :param length: Length in bytes (1-4)
""" """
# NAC3TODO assert length > 0 assert length > 0
# NAC3TODO assert length <= 4 assert length <= 4
self.bus.set_config_mu(SPI_CONFIG, 16, self.bus.set_config_mu(SPI_CONFIG, 16,
SPIT_DDS_WR, self.chip_select) SPIT_DDS_WR, self.chip_select)
self.bus.write((addr | ((length - 1) << 13)) << 16) self.bus.write((addr | ((length - 1) << 13)) << 16)
@ -80,8 +80,8 @@ class AD9912:
:param length: Length in bytes (1-4) :param length: Length in bytes (1-4)
:return: Data read :return: Data read
""" """
# NAC3TODO assert length > 0 assert length > 0
# NAC3TODO assert length <= 4 assert length <= 4
self.bus.set_config_mu(SPI_CONFIG, 16, self.bus.set_config_mu(SPI_CONFIG, 16,
SPIT_DDS_WR, self.chip_select) SPIT_DDS_WR, self.chip_select)
self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16) self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16)

2
artiq/coredevice/fastino.py
View File

@ -274,7 +274,7 @@ class Fastino:
while gain > 1 << gain_exponent: while gain > 1 << gain_exponent:
gain_exponent += 1 gain_exponent += 1
gain_exponent += order*rate_exponent gain_exponent += order*rate_exponent
# NAC3TODO assert gain_exponent <= order*16 assert gain_exponent <= order*16
self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent) self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent)
return rate_mantissa << rate_exponent return rate_mantissa << rate_exponent

2
artiq/coredevice/urukul.py
View File

@ -411,7 +411,7 @@ class CPLD:
""" """
ftw_max = 1 << 4 ftw_max = 1 << 4
ftw = ftw_max // div ftw = ftw_max // div
# NAC3TODO assert ftw * div == ftw_max assert ftw * div == ftw_max
if self.sync.is_some(): if self.sync.is_some():
self.sync.unwrap().set_mu(ftw) self.sync.unwrap().set_mu(ftw)

8
flake.lock
View File

@ -45,11 +45,11 @@
"nixpkgs": "nixpkgs" "nixpkgs": "nixpkgs"
}, },
"locked": { "locked": {
"lastModified": 1648348280, "lastModified": 1648508200,
"narHash": "sha256-zPotCWV0l1EgxJp/1MIUNvhCiMoEmpn5fnARrLNa6Ak=", "narHash": "sha256-8ohq5rj5rV9xyHDbU0oT/2CXT917XQYtxU92GIC+43s=",
"ref": "master", "ref": "master",
"rev": "bed33a7421b2c8f6b595f8feaa602de041bcc14f", "rev": "a38cc0444456392fba6949367e4073ee9df149bf",
"revCount": 695, "revCount": 705,
"type": "git", "type": "git",
"url": "https://git.m-labs.hk/m-labs/nac3.git" "url": "https://git.m-labs.hk/m-labs/nac3.git"
}, },