From b1cfd343eb7c0362337ff9633be086f7ec84c5a2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 29 Mar 2022 08:49:43 +0800 Subject: [PATCH] update NAC3 --- artiq/coredevice/ad53xx.py | 4 ++-- artiq/coredevice/ad9912.py | 8 ++++---- artiq/coredevice/fastino.py | 2 +- artiq/coredevice/urukul.py | 2 +- flake.lock | 8 ++++---- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/artiq/coredevice/ad53xx.py b/artiq/coredevice/ad53xx.py index 26bc0d6c0..293776b1c 100644 --- a/artiq/coredevice/ad53xx.py +++ b/artiq/coredevice/ad53xx.py @@ -381,8 +381,8 @@ class AD53xx: gain_err = voltage_to_mu(vfs, self.offset_dacs, self.vref) - ( offset_err + 0xffff) - # NAC3TODO assert offset_err <= 0 - # NAC3TODO assert gain_err >= 0 + assert offset_err <= 0 + assert gain_err >= 0 self.core.break_realtime() self.write_offset_mu(channel, 0x8000-offset_err) diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py index 5a4af26b2..7f81ef400 100644 --- a/artiq/coredevice/ad9912.py +++ b/artiq/coredevice/ad9912.py @@ -62,8 +62,8 @@ class AD9912: :param data: Data to be written: int32 :param length: Length in bytes (1-4) """ - # NAC3TODO assert length > 0 - # NAC3TODO assert length <= 4 + assert length > 0 + assert length <= 4 self.bus.set_config_mu(SPI_CONFIG, 16, SPIT_DDS_WR, self.chip_select) self.bus.write((addr | ((length - 1) << 13)) << 16) @@ -80,8 +80,8 @@ class AD9912: :param length: Length in bytes (1-4) :return: Data read """ - # NAC3TODO assert length > 0 - # NAC3TODO assert length <= 4 + assert length > 0 + assert length <= 4 self.bus.set_config_mu(SPI_CONFIG, 16, SPIT_DDS_WR, self.chip_select) self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16) diff --git a/artiq/coredevice/fastino.py b/artiq/coredevice/fastino.py index 6e455a324..995d20b6b 100644 --- a/artiq/coredevice/fastino.py +++ b/artiq/coredevice/fastino.py @@ -274,7 +274,7 @@ class Fastino: while gain > 1 << gain_exponent: gain_exponent += 1 gain_exponent += order*rate_exponent - # NAC3TODO assert gain_exponent <= order*16 + assert gain_exponent <= order*16 self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent) return rate_mantissa << rate_exponent diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py index d28dff76c..769c31ab3 100644 --- a/artiq/coredevice/urukul.py +++ b/artiq/coredevice/urukul.py @@ -411,7 +411,7 @@ class CPLD: """ ftw_max = 1 << 4 ftw = ftw_max // div - # NAC3TODO assert ftw * div == ftw_max + assert ftw * div == ftw_max if self.sync.is_some(): self.sync.unwrap().set_mu(ftw) diff --git a/flake.lock b/flake.lock index 563e227e5..c8e23be43 100644 --- a/flake.lock +++ b/flake.lock @@ -45,11 +45,11 @@ "nixpkgs": "nixpkgs" }, "locked": { - "lastModified": 1648348280, - "narHash": "sha256-zPotCWV0l1EgxJp/1MIUNvhCiMoEmpn5fnARrLNa6Ak=", + "lastModified": 1648508200, + "narHash": "sha256-8ohq5rj5rV9xyHDbU0oT/2CXT917XQYtxU92GIC+43s=", "ref": "master", - "rev": "bed33a7421b2c8f6b595f8feaa602de041bcc14f", - "revCount": 695, + "rev": "a38cc0444456392fba6949367e4073ee9df149bf", + "revCount": 705, "type": "git", "url": "https://git.m-labs.hk/m-labs/nac3.git" },