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update NAC3
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parent
69cda517f6
commit
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@ -381,8 +381,8 @@ class AD53xx:
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gain_err = voltage_to_mu(vfs, self.offset_dacs, self.vref) - (
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offset_err + 0xffff)
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# NAC3TODO assert offset_err <= 0
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# NAC3TODO assert gain_err >= 0
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assert offset_err <= 0
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assert gain_err >= 0
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self.core.break_realtime()
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self.write_offset_mu(channel, 0x8000-offset_err)
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@ -62,8 +62,8 @@ class AD9912:
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:param data: Data to be written: int32
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:param length: Length in bytes (1-4)
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"""
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# NAC3TODO assert length > 0
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# NAC3TODO assert length <= 4
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assert length > 0
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assert length <= 4
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self.bus.set_config_mu(SPI_CONFIG, 16,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | ((length - 1) << 13)) << 16)
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@ -80,8 +80,8 @@ class AD9912:
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:param length: Length in bytes (1-4)
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:return: Data read
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"""
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# NAC3TODO assert length > 0
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# NAC3TODO assert length <= 4
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assert length > 0
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assert length <= 4
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self.bus.set_config_mu(SPI_CONFIG, 16,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16)
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@ -274,7 +274,7 @@ class Fastino:
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while gain > 1 << gain_exponent:
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gain_exponent += 1
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gain_exponent += order*rate_exponent
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# NAC3TODO assert gain_exponent <= order*16
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assert gain_exponent <= order*16
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self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent)
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return rate_mantissa << rate_exponent
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@ -411,7 +411,7 @@ class CPLD:
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"""
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ftw_max = 1 << 4
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ftw = ftw_max // div
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# NAC3TODO assert ftw * div == ftw_max
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assert ftw * div == ftw_max
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if self.sync.is_some():
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self.sync.unwrap().set_mu(ftw)
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8
flake.lock
generated
8
flake.lock
generated
@ -45,11 +45,11 @@
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"nixpkgs": "nixpkgs"
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},
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"locked": {
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"lastModified": 1648348280,
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"narHash": "sha256-zPotCWV0l1EgxJp/1MIUNvhCiMoEmpn5fnARrLNa6Ak=",
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"lastModified": 1648508200,
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"narHash": "sha256-8ohq5rj5rV9xyHDbU0oT/2CXT917XQYtxU92GIC+43s=",
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"ref": "master",
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"rev": "bed33a7421b2c8f6b595f8feaa602de041bcc14f",
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"revCount": 695,
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"rev": "a38cc0444456392fba6949367e4073ee9df149bf",
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"revCount": 705,
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"type": "git",
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"url": "https://git.m-labs.hk/m-labs/nac3.git"
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},
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