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kc705: cleanup
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parent
7c4eed7a11
commit
a0fd5261ea
artiq/gateware
drtio/transceiver
targets
@ -228,13 +228,6 @@ class GTX_20X(Module):
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p_RXCDR_PH_RESET_ON_EIDLE=0b0,
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p_RXCDR_LOCK_CFG=0b010101,
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# # RX Initialization and Reset Attributes
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# p_RXCDRFREQRESET_TIME=0b00001,
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# p_RXCDRPHRESET_TIME=0b00001,
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# p_RXISCANRESET_TIME=0b00001,
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# p_RXPCSRESET_TIME=0b00001,
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# p_RXPMARESET_TIME=0b00011,
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# Pads
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i_GTXRXP=rx_pads.p,
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i_GTXRXN=rx_pads.n,
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@ -1,9 +1,7 @@
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from math import ceil
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from functools import reduce
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from operator import add
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from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import WaitTimer
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from migen.genlib.fsm import FSM
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@ -137,7 +135,7 @@ class GTXInit(Module):
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If(Xxresetdone, NextState("DELAY_ALIGN"))
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)
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# State(s) exclusive to Auto Mode:
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# States exclusive to Auto Mode:
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if mode == "single":
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# Start delay alignment (pulse)
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startup_fsm.act("DELAY_ALIGN",
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@ -161,7 +159,7 @@ class GTXInit(Module):
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If(Xxphaligndone_rising, NextState("READY"))
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)
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# State(s) exclusive to Manual Mode:
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# States exclusive to Manual Mode:
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else:
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# Start delay alignment (hold)
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startup_fsm.act("DELAY_ALIGN",
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@ -9,8 +9,8 @@ from migen.build.xilinx.ise import XilinxISEToolchain
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from misoc.cores import spi as spi_csr
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from misoc.cores import gpio
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from misoc.integration.builder import *
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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@ -1,7 +1,6 @@
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#!/usr/bin/env python3
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import argparse
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import os
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from migen import *
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from migen.build.generic_platform import *
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@ -21,9 +20,6 @@ from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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# DEBUG
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from microscope import *
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class Satellite(BaseSoC):
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mem_map = {
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