diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py
index a977d2b4c..a2da39822 100644
--- a/artiq/gateware/drtio/transceiver/gtx_7series.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series.py
@@ -228,13 +228,6 @@ class GTX_20X(Module):
                 p_RXCDR_PH_RESET_ON_EIDLE=0b0,
                 p_RXCDR_LOCK_CFG=0b010101,
 
-                # # RX Initialization and Reset Attributes
-                # p_RXCDRFREQRESET_TIME=0b00001,
-                # p_RXCDRPHRESET_TIME=0b00001,
-                # p_RXISCANRESET_TIME=0b00001,
-                # p_RXPCSRESET_TIME=0b00001,
-                # p_RXPMARESET_TIME=0b00011,
-
                 # Pads
                 i_GTXRXP=rx_pads.p,
                 i_GTXRXN=rx_pads.n,
diff --git a/artiq/gateware/drtio/transceiver/gtx_7series_init.py b/artiq/gateware/drtio/transceiver/gtx_7series_init.py
index 0536cf47a..70c69a19c 100644
--- a/artiq/gateware/drtio/transceiver/gtx_7series_init.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series_init.py
@@ -1,9 +1,7 @@
 from math import ceil
-from functools import reduce
-from operator import add
 
 from migen import *
-from migen.genlib.cdc import MultiReg, PulseSynchronizer
+from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import WaitTimer
 from migen.genlib.fsm import FSM
 
@@ -137,7 +135,7 @@ class GTXInit(Module):
                 If(Xxresetdone, NextState("DELAY_ALIGN"))
             )
 
-        # State(s) exclusive to Auto Mode:
+        # States exclusive to Auto Mode:
         if mode == "single":
             # Start delay alignment (pulse)
             startup_fsm.act("DELAY_ALIGN",
@@ -161,7 +159,7 @@ class GTXInit(Module):
                 If(Xxphaligndone_rising, NextState("READY"))
             )
 
-        # State(s) exclusive to Manual Mode:
+        # States exclusive to Manual Mode:
         else:
             # Start delay alignment (hold)
             startup_fsm.act("DELAY_ALIGN",
diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py
index 0cf74562a..78d5d054b 100755
--- a/artiq/gateware/targets/kc705_drtio_master.py
+++ b/artiq/gateware/targets/kc705_drtio_master.py
@@ -9,8 +9,8 @@ from migen.build.xilinx.ise import XilinxISEToolchain
 
 from misoc.cores import spi as spi_csr
 from misoc.cores import gpio
+from misoc.integration.builder import *
 from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
-from misoc.integration.builder import builder_args, builder_argdict
 
 from artiq.gateware.amp import AMPSoC
 from artiq.gateware import rtio
diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py
index 4f7fbb361..4ff346fdf 100755
--- a/artiq/gateware/targets/kc705_drtio_satellite.py
+++ b/artiq/gateware/targets/kc705_drtio_satellite.py
@@ -1,7 +1,6 @@
 #!/usr/bin/env python3
 
 import argparse
-import os
 
 from migen import *
 from migen.build.generic_platform import *
@@ -21,9 +20,6 @@ from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import *
 from artiq.build_soc import *
 
-# DEBUG
-from microscope import *
-
 
 class Satellite(BaseSoC):
     mem_map = {