2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 11:18:27 +08:00

gateware/suservo: fix profile no. in test

Follow-up/Test update for 9d49302.
This commit is contained in:
occheung 2022-01-11 14:20:44 +08:00
parent d7dd75e833
commit 9eee0e5a7b

View File

@ -79,7 +79,7 @@ def main():
data = [] data = []
run_simulation(tb, [tb.log(data), run(tb)], vcd_name="dds.vcd") run_simulation(tb, [tb.log(data), run(tb)], vcd_name="dds.vcd")
assert data[-1][1] == [[0xe, 0x40 | i, 0x30 | i, 0x20 | i] for i in assert data[-1][1] == [[0x15, 0x40 | i, 0x30 | i, 0x20 | i] for i in
range(4)] range(4)]