mirror of https://github.com/m-labs/artiq.git
drtio: add external TSC to repeater
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parent
5f20d79408
commit
839f748a1d
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@ -181,13 +181,13 @@ class DRTIOMaster(Module):
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class DRTIORepeater(Module):
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class DRTIORepeater(Module):
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def __init__(self, chanif):
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def __init__(self, tsc, chanif):
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self.submodules.link_layer = link_layer.LinkLayer(
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self.submodules.link_layer = link_layer.LinkLayer(
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chanif.encoder, chanif.decoders)
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(self.link_layer)
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self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(tsc, self.link_layer)
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self.submodules.aux_controller = aux_controller.AuxController(
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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self.link_layer)
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@ -9,7 +9,7 @@ from artiq.gateware.drtio.rt_serializer import *
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class RTPacketRepeater(Module):
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class RTPacketRepeater(Module):
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def __init__(self, link_layer):
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def __init__(self, tsc, link_layer):
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# CRI target interface in rtio domain
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# CRI target interface in rtio domain
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self.cri = cri.Interface()
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self.cri = cri.Interface()
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@ -24,7 +24,6 @@ class RTPacketRepeater(Module):
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# set_time interface, in rtio domain
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# set_time interface, in rtio domain
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self.set_time_stb = Signal()
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self.set_time_stb = Signal()
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self.set_time_ack = Signal()
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self.set_time_ack = Signal()
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self.tsc_value = Signal(64)
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# # #
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# # #
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@ -44,7 +43,7 @@ class RTPacketRepeater(Module):
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# TSC sync
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# TSC sync
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tsc_value = Signal(64)
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tsc_value = Signal(64)
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tsc_value_load = Signal()
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tsc_value_load = Signal()
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self.sync.rtio += If(tsc_value_load, tsc_value.eq(self.tsc_value))
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self.sync.rtio += If(tsc_value_load, tsc_value.eq(tsc.coarse_ts))
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# Write buffer and extra data count
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# Write buffer and extra data count
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wb_timestamp = Signal(64)
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wb_timestamp = Signal(64)
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@ -11,20 +11,23 @@ from artiq.gateware.drtio.rt_packet_repeater import RTPacketRepeater
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def create_dut(nwords):
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def create_dut(nwords):
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pt = PacketInterface("s2m", nwords*8)
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pt = PacketInterface("s2m", nwords*8)
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pr = PacketInterface("m2s", nwords*8)
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pr = PacketInterface("m2s", nwords*8)
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ts = Signal(64)
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dut = ClockDomainsRenamer({"rtio": "sys", "rtio_rx": "sys"})(
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dut = ClockDomainsRenamer({"rtio": "sys", "rtio_rx": "sys"})(
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RTPacketRepeater(SimpleNamespace(
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RTPacketRepeater(
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rx_rt_frame=pt.frame, rx_rt_data=pt.data,
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SimpleNamespace(coarse_ts=ts),
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tx_rt_frame=pr.frame, tx_rt_data=pr.data)))
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SimpleNamespace(
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return pt, pr, dut
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rx_rt_frame=pt.frame, rx_rt_data=pt.data,
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tx_rt_frame=pr.frame, tx_rt_data=pr.data)))
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return pt, pr, ts, dut
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class TestRepeater(unittest.TestCase):
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class TestRepeater(unittest.TestCase):
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def test_set_time(self):
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def test_set_time(self):
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nwords = 2
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nwords = 2
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pt, pr, dut = create_dut(nwords)
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pt, pr, ts, dut = create_dut(nwords)
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def send():
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def send():
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yield dut.tsc_value.eq(0x12345678)
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yield ts.eq(0x12345678)
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yield dut.set_time_stb.eq(1)
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yield dut.set_time_stb.eq(1)
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while not (yield dut.set_time_ack):
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while not (yield dut.set_time_ack):
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yield
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yield
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@ -55,7 +58,7 @@ class TestRepeater(unittest.TestCase):
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]
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]
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for nwords in range(1, 8):
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for nwords in range(1, 8):
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pt, pr, dut = create_dut(nwords)
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pt, pr, ts, dut = create_dut(nwords)
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def send():
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def send():
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for channel, timestamp, address, data in test_writes:
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for channel, timestamp, address, data in test_writes:
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@ -89,7 +92,7 @@ class TestRepeater(unittest.TestCase):
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def test_buffer_space(self):
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def test_buffer_space(self):
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for nwords in range(1, 8):
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for nwords in range(1, 8):
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pt, pr, dut = create_dut(nwords)
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pt, pr, ts, dut = create_dut(nwords)
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def send_requests():
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def send_requests():
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for i in range(10):
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for i in range(10):
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