From 839f748a1dda4089a23e933945f2dd1081b83e85 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 5 Sep 2018 15:55:20 +0800 Subject: [PATCH] drtio: add external TSC to repeater --- artiq/gateware/drtio/core.py | 4 ++-- artiq/gateware/drtio/rt_packet_repeater.py | 5 ++--- .../test/drtio/test_rt_packet_repeater.py | 19 +++++++++++-------- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py index 47a56ce0c..13afbab46 100644 --- a/artiq/gateware/drtio/core.py +++ b/artiq/gateware/drtio/core.py @@ -181,13 +181,13 @@ class DRTIOMaster(Module): class DRTIORepeater(Module): - def __init__(self, chanif): + def __init__(self, tsc, chanif): self.submodules.link_layer = link_layer.LinkLayer( chanif.encoder, chanif.decoders) self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready) self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx") - self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(self.link_layer) + self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(tsc, self.link_layer) self.submodules.aux_controller = aux_controller.AuxController( self.link_layer) diff --git a/artiq/gateware/drtio/rt_packet_repeater.py b/artiq/gateware/drtio/rt_packet_repeater.py index 081d444a3..379a445ec 100644 --- a/artiq/gateware/drtio/rt_packet_repeater.py +++ b/artiq/gateware/drtio/rt_packet_repeater.py @@ -9,7 +9,7 @@ from artiq.gateware.drtio.rt_serializer import * class RTPacketRepeater(Module): - def __init__(self, link_layer): + def __init__(self, tsc, link_layer): # CRI target interface in rtio domain self.cri = cri.Interface() @@ -24,7 +24,6 @@ class RTPacketRepeater(Module): # set_time interface, in rtio domain self.set_time_stb = Signal() self.set_time_ack = Signal() - self.tsc_value = Signal(64) # # # @@ -44,7 +43,7 @@ class RTPacketRepeater(Module): # TSC sync tsc_value = Signal(64) tsc_value_load = Signal() - self.sync.rtio += If(tsc_value_load, tsc_value.eq(self.tsc_value)) + self.sync.rtio += If(tsc_value_load, tsc_value.eq(tsc.coarse_ts)) # Write buffer and extra data count wb_timestamp = Signal(64) diff --git a/artiq/gateware/test/drtio/test_rt_packet_repeater.py b/artiq/gateware/test/drtio/test_rt_packet_repeater.py index c778d1724..d348a5efc 100644 --- a/artiq/gateware/test/drtio/test_rt_packet_repeater.py +++ b/artiq/gateware/test/drtio/test_rt_packet_repeater.py @@ -11,20 +11,23 @@ from artiq.gateware.drtio.rt_packet_repeater import RTPacketRepeater def create_dut(nwords): pt = PacketInterface("s2m", nwords*8) pr = PacketInterface("m2s", nwords*8) + ts = Signal(64) dut = ClockDomainsRenamer({"rtio": "sys", "rtio_rx": "sys"})( - RTPacketRepeater(SimpleNamespace( - rx_rt_frame=pt.frame, rx_rt_data=pt.data, - tx_rt_frame=pr.frame, tx_rt_data=pr.data))) - return pt, pr, dut + RTPacketRepeater( + SimpleNamespace(coarse_ts=ts), + SimpleNamespace( + rx_rt_frame=pt.frame, rx_rt_data=pt.data, + tx_rt_frame=pr.frame, tx_rt_data=pr.data))) + return pt, pr, ts, dut class TestRepeater(unittest.TestCase): def test_set_time(self): nwords = 2 - pt, pr, dut = create_dut(nwords) + pt, pr, ts, dut = create_dut(nwords) def send(): - yield dut.tsc_value.eq(0x12345678) + yield ts.eq(0x12345678) yield dut.set_time_stb.eq(1) while not (yield dut.set_time_ack): yield @@ -55,7 +58,7 @@ class TestRepeater(unittest.TestCase): ] for nwords in range(1, 8): - pt, pr, dut = create_dut(nwords) + pt, pr, ts, dut = create_dut(nwords) def send(): for channel, timestamp, address, data in test_writes: @@ -89,7 +92,7 @@ class TestRepeater(unittest.TestCase): def test_buffer_space(self): for nwords in range(1, 8): - pt, pr, dut = create_dut(nwords) + pt, pr, ts, dut = create_dut(nwords) def send_requests(): for i in range(10):