sayma,kasli: use new pin names

artiq/gateware/drtio/transceiver/gth_ultrascale.py

@@ -14,7 +14,7 @@ from artiq.gateware.drtio.transceiver.gth_ultrascale_init import *
 
 
 class GTHSingle(Module):
-    def __init__(self, refclk, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, dw, mode):
+    def __init__(self, refclk, pads, sys_clk_freq, rtio_clk_freq, dw, mode):
         assert (dw == 20) or (dw == 40)
         assert mode in ["master", "slave"]
 
@@ -167,10 +167,10 @@ class GTHSingle(Module):
                 i_RXELECIDLEMODE=0b11,
 
                 # Pads
-                i_GTHRXP=rx_pads.p,
+                i_GTHRXP=pads.rxp,
-                i_GTHRXN=rx_pads.n,
+                i_GTHRXN=pads.rxn,
-                o_GTHTXP=tx_pads.p,
+                o_GTHTXP=pads.txp,
-                o_GTHTXN=tx_pads.n
+                o_GTHTXN=pads.txn
             )
 
         self.submodules += [
@@ -222,8 +222,8 @@ class GTHSingle(Module):
 
 
 class GTH(Module, TransceiverInterface):
-    def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, dw=20, master=0):
+    def __init__(self, clock_pads, data_pads, sys_clk_freq, rtio_clk_freq, dw=20, master=0):
-        self.nchannels = nchannels = len(tx_pads)
+        self.nchannels = nchannels = len(data_pads)
         self.gths = []
 
         # # #
@@ -239,7 +239,7 @@ class GTH(Module, TransceiverInterface):
         channel_interfaces = []
         for i in range(nchannels):
             mode = "master" if i == master else "slave"
-            gth = GTHSingle(refclk, tx_pads[i], rx_pads[i], sys_clk_freq, rtio_clk_freq, dw, mode)
+            gth = GTHSingle(refclk, data_pads[i], sys_clk_freq, rtio_clk_freq, dw, mode)
             if mode == "master":
                 self.comb += rtio_tx_clk.eq(gth.cd_rtio_tx.clk)
             else:

artiq/gateware/drtio/transceiver/gtp_7series.py

@@ -12,7 +12,7 @@ from artiq.gateware.drtio.transceiver.gtp_7series_init import *
 
 
 class GTPSingle(Module):
-    def __init__(self, qpll_channel, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, mode):
+    def __init__(self, qpll_channel, pads, sys_clk_freq, rtio_clk_freq, mode):
         if mode != "master":
             raise NotImplementedError
         self.submodules.encoder = encoder = ClockDomainsRenamer("rtio_tx")(
@@ -163,10 +163,10 @@ class GTPSingle(Module):
                 o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
 
                 # Pads
-                i_GTPRXP=rx_pads.p,
+                i_GTPRXP=pads.rxp,
-                i_GTPRXN=rx_pads.n,
+                i_GTPRXN=pads.rxn,
-                o_GTPTXP=tx_pads.p,
+                o_GTPTXP=pads.txp,
-                o_GTPTXN=tx_pads.n
+                o_GTPTXN=pads.txn
             )
 
         # tx clocking
@@ -215,8 +215,8 @@ class GTPSingle(Module):
 
 
 class GTP(Module, TransceiverInterface):
-    def __init__(self, qpll_channel, tx_pads, rx_pads, sys_clk_freq, rtio_clk_freq, master=0):
+    def __init__(self, qpll_channel, data_pads, sys_clk_freq, rtio_clk_freq, master=0):
-        self.nchannels = nchannels = len(tx_pads)
+        self.nchannels = nchannels = len(data_pads)
         self.gtps = []
         if nchannels >= 1:
             raise NotImplementedError
@@ -227,7 +227,7 @@ class GTP(Module, TransceiverInterface):
         channel_interfaces = []
         for i in range(nchannels):
             mode = "master" if i == master else "slave"
-            gtp = GTPSingle(qpll_channel, tx_pads[i], rx_pads[i], sys_clk_freq, rtio_clk_freq, mode)
+            gtp = GTPSingle(qpll_channel, data_pads[i], sys_clk_freq, rtio_clk_freq, mode)
             if mode == "master":
                 self.comb += rtio_tx_clk.eq(gtp.cd_rtio_tx.clk)
             else:

artiq/gateware/targets/kasli.py

@@ -30,14 +30,14 @@ class _RTIOCRG(Module, AutoCSR):
         self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
 
         rtio_external_clk = Signal()
-        clk_fpgaio_se = Signal()
+        clk_synth_se = Signal()
-        clk_fpgaio = platform.request("clk_fpgaio")  # from Si5324
+        clk_synth = platform.request("si5324_clkout_fabric")
-        platform.add_period_constraint(clk_fpgaio.p, 8.0)
+        platform.add_period_constraint(clk_synth.p, 8.0)
         self.specials += [
-                Instance("IBUFGDS",
+            Instance("IBUFGDS",
-                    p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
+                p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
-                    i_I=clk_fpgaio.p, i_IB=clk_fpgaio.n, o_O=clk_fpgaio_se),
+                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
-                Instance("BUFG", i_I=clk_fpgaio_se, o_O=rtio_external_clk),
+            Instance("BUFG", i_I=clk_synth_se, o_O=rtio_external_clk),
         ]
 
         pll_locked = Signal()
@@ -169,8 +169,8 @@ class Opticlock(_KasliBase):
                 rtio_channels.append(rtio.Channel.from_phy(phy))
 
         for i in (1, 2):
-            sfp = platform.request("sfp", i)
+            sfp_ctl = platform.request("sfp_ctl", i)
-            phy = ttl_simple.Output(sfp.led)
+            phy = ttl_simple.Output(sfp_ctl.led)
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy))
 

artiq/gateware/targets/sayma_amc_drtio_master.py

@@ -61,8 +61,7 @@ class Master(MiniSoC, AMPSoC):
         self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
         self.submodules.transceiver = gth_ultrascale.GTH(
             clock_pads=platform.request("si5324_clkout"),
-            tx_pads=[platform.request("sfp_tx", 0)],
+            data_pads=[platform.request("sfp", 0)],
-            rx_pads=[platform.request("sfp_rx", 0)],
             sys_clk_freq=self.clk_freq,
             rtio_clk_freq=rtio_clk_freq)
 

artiq/gateware/targets/sayma_amc_drtio_satellite.py

@@ -63,8 +63,7 @@ class Satellite(BaseSoC):
         self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
         self.submodules.transceiver = gth_ultrascale.GTH(
             clock_pads=platform.request("si5324_clkout"),
-            tx_pads=[platform.request("sfp_tx", 0)],
+            data_pads=[platform.request("sfp", 0)],
-            rx_pads=[platform.request("sfp_rx", 0)],
             sys_clk_freq=self.clk_freq,
             rtio_clk_freq=rtio_clk_freq)
         rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})