mirror of https://github.com/m-labs/artiq.git
252 lines
9.2 KiB
Python
252 lines
9.2 KiB
Python
from functools import reduce
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from operator import or_
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores.code_8b10b import Encoder, Decoder
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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from artiq.gateware.drtio.transceiver.clock_aligner import BruteforceClockAligner
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from artiq.gateware.drtio.transceiver.gtp_7series_init import *
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class GTPSingle(Module):
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def __init__(self, qpll_channel, pads, sys_clk_freq, rtio_clk_freq, mode):
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if mode != "master":
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raise NotImplementedError
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self.submodules.encoder = encoder = ClockDomainsRenamer("rtio_tx")(
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Encoder(2, True))
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self.submodules.decoders = decoders = [ClockDomainsRenamer("rtio_rx")(
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(Decoder(True))) for _ in range(2)]
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self.rx_ready = Signal()
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# transceiver direct clock outputs
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# useful to specify clock constraints in a way palatable to Vivado
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self.txoutclk = Signal()
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self.rxoutclk = Signal()
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# # #
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# TX generates RTIO clock, init must be in system domain
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tx_init = GTPTXInit(sys_clk_freq)
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# RX receives restart commands from RTIO domain
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rx_init = ClockDomainsRenamer("rtio_tx")(GTPRXInit(rtio_clk_freq))
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self.submodules += tx_init, rx_init
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self.comb += [
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qpll_channel.reset.eq(tx_init.pllreset),
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tx_init.plllock.eq(qpll_channel.lock),
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rx_init.plllock.eq(qpll_channel.lock),
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]
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txdata = Signal(20)
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rxdata = Signal(20)
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rxphaligndone = Signal()
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self.specials += \
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Instance("GTPE2_CHANNEL",
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# Reset modes
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i_GTRESETSEL=0,
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i_RESETOVRD=0,
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# DRP
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i_DRPADDR=rx_init.drpaddr,
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i_DRPCLK=ClockSignal("rtio_tx"),
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i_DRPDI=rx_init.drpdi,
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o_DRPDO=rx_init.drpdo,
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i_DRPEN=rx_init.drpen,
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o_DRPRDY=rx_init.drprdy,
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i_DRPWE=rx_init.drpwe,
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# PMA Attributes
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p_PMA_RSV=0x333,
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p_PMA_RSV2=0x2040,
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p_PMA_RSV3=0,
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p_PMA_RSV4=0,
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p_RX_BIAS_CFG=0b0000111100110011,
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p_RX_CM_SEL=0b01,
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p_RX_CM_TRIM=0b1010,
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p_RX_OS_CFG=0b10000000,
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p_RXLPM_IPCM_CFG=1,
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i_RXELECIDLEMODE=0b11,
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i_RXOSINTCFG=0b0010,
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i_RXOSINTEN=1,
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# Power-Down Attributes
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p_PD_TRANS_TIME_FROM_P2=0x3c,
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p_PD_TRANS_TIME_NONE_P2=0x3c,
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p_PD_TRANS_TIME_TO_P2=0x64,
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# QPLL
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i_PLL0CLK=qpll_channel.clk,
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i_PLL0REFCLK=qpll_channel.refclk,
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# TX clock
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p_TXBUF_EN="FALSE",
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=self.txoutclk,
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p_TXOUT_DIV=2,
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i_TXSYSCLKSEL=0b00,
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i_TXOUTCLKSEL=0b11,
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# TX Startup/Reset
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i_GTTXRESET=tx_init.gttxreset,
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o_TXRESETDONE=tx_init.txresetdone,
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p_TXSYNC_OVRD=1,
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i_TXDLYSRESET=tx_init.txdlysreset,
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o_TXDLYSRESETDONE=tx_init.txdlysresetdone,
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i_TXPHINIT=tx_init.txphinit,
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o_TXPHINITDONE=tx_init.txphinitdone,
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i_TXPHALIGNEN=1,
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i_TXPHALIGN=tx_init.txphalign,
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o_TXPHALIGNDONE=tx_init.txphaligndone,
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i_TXDLYEN=tx_init.txdlyen,
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i_TXUSERRDY=tx_init.txuserrdy,
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# TX data
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p_TX_DATA_WIDTH=20,
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i_TXCHARDISPMODE=Cat(txdata[9], txdata[19]),
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i_TXCHARDISPVAL=Cat(txdata[8], txdata[18]),
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i_TXDATA=Cat(txdata[:8], txdata[10:18]),
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i_TXUSRCLK=ClockSignal("rtio_tx"),
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i_TXUSRCLK2=ClockSignal("rtio_tx"),
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# TX electrical
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i_TXBUFDIFFCTRL=0b100,
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i_TXDIFFCTRL=0b1000,
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# RX Startup/Reset
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i_GTRXRESET=rx_init.gtrxreset,
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o_RXRESETDONE=rx_init.rxresetdone,
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i_RXDLYSRESET=rx_init.rxdlysreset,
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o_RXDLYSRESETDONE=rx_init.rxdlysresetdone,
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o_RXPHALIGNDONE=rxphaligndone,
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i_RXSYNCALLIN=rxphaligndone,
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i_RXUSERRDY=rx_init.rxuserrdy,
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i_RXSYNCIN=0,
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i_RXSYNCMODE=1,
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p_RXSYNC_MULTILANE=0,
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p_RXSYNC_OVRD=0,
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o_RXSYNCDONE=rx_init.rxsyncdone,
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p_RXPMARESET_TIME=0b11,
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o_RXPMARESETDONE=rx_init.rxpmaresetdone,
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# RX clock
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p_RX_CLK25_DIV=5,
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p_TX_CLK25_DIV=5,
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p_RX_XCLK_SEL="RXUSR",
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p_RXOUT_DIV=2,
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i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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i_RXUSRCLK2=ClockSignal("rtio_rx"),
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p_RXCDR_CFG=0x0000107FE206001041010,
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p_RXPI_CFG1=1,
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p_RXPI_CFG2=1,
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# RX Clock Correction Attributes
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p_CLK_CORRECT_USE="FALSE",
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# RX data
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p_RXBUF_EN="FALSE",
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p_RXDLY_CFG=0x001f,
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p_RXDLY_LCFG=0x030,
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p_RXPHDLY_CFG=0x084020,
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p_RXPH_CFG=0xc00002,
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p_RX_DATA_WIDTH=20,
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i_RXCOMMADETEN=1,
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i_RXDLYBYPASS=0,
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i_RXDDIEN=1,
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o_RXDISPERR=Cat(rxdata[9], rxdata[19]),
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o_RXCHARISK=Cat(rxdata[8], rxdata[18]),
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o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
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# Pads
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i_GTPRXP=pads.rxp,
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i_GTPRXN=pads.rxn,
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o_GTPTXP=pads.txp,
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o_GTPTXN=pads.txn
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)
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# tx clocking
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tx_reset_deglitched = Signal()
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tx_reset_deglitched.attr.add("no_retiming")
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.clock_domains.cd_rtio_tx = ClockDomain()
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if mode == "master":
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txoutclk_bufg = Signal()
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txoutclk_bufr = Signal()
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tx_bufr_div = 150.e6/rtio_clk_freq
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assert tx_bufr_div == int(tx_bufr_div)
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self.specials += [
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Instance("BUFG", i_I=self.txoutclk, o_O=txoutclk_bufg),
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Instance("BUFR", i_I=txoutclk_bufg, o_O=txoutclk_bufr,
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i_CE=1, p_BUFR_DIVIDE=str(int(tx_bufr_div))),
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Instance("BUFG", i_I=txoutclk_bufr, o_O=self.cd_rtio_tx.clk)
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]
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self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)
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# rx clocking
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rx_reset_deglitched = Signal()
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rx_reset_deglitched.attr.add("no_retiming")
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self.sync.rtio_tx += rx_reset_deglitched.eq(~rx_init.done)
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self.clock_domains.cd_rtio_rx = ClockDomain()
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self.specials += [
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Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx.clk),
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AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched)
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]
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# tx data
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self.comb += txdata.eq(Cat(*[encoder.output[i] for i in range(2)]))
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# rx data
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for i in range(2):
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self.comb += decoders[i].input.eq(rxdata[10*i:10*(i+1)])
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# clock alignment
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clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq, check_period=10e-3)
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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rx_init.restart.eq(clock_aligner.restart),
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self.rx_ready.eq(clock_aligner.ready)
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]
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class GTP(Module, TransceiverInterface):
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def __init__(self, qpll_channel, data_pads, sys_clk_freq, rtio_clk_freq, master=0):
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self.nchannels = nchannels = len(data_pads)
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self.gtps = []
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if nchannels >= 1:
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raise NotImplementedError
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# # #
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rtio_tx_clk = Signal()
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channel_interfaces = []
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for i in range(nchannels):
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mode = "master" if i == master else "slave"
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gtp = GTPSingle(qpll_channel, data_pads[i], sys_clk_freq, rtio_clk_freq, mode)
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if mode == "master":
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self.comb += rtio_tx_clk.eq(gtp.cd_rtio_tx.clk)
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else:
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self.comb += gtp.cd_rtio_tx.clk.eq(rtio_tx_clk)
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self.gtps.append(gtp)
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setattr(self.submodules, "gtp"+str(i), gtp)
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channel_interface = ChannelInterface(gtp.encoder, gtp.decoders)
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self.comb += channel_interface.rx_ready.eq(gtp.rx_ready)
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channel_interfaces.append(channel_interface)
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TransceiverInterface.__init__(self, channel_interfaces)
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self.comb += [
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self.cd_rtio.clk.eq(self.gtps[master].cd_rtio_tx.clk),
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self.cd_rtio.rst.eq(reduce(or_, [gtp.cd_rtio_tx.rst for gtp in self.gtps]))
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]
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for i in range(nchannels):
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self.comb += [
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getattr(self, "cd_rtio_rx" + str(i)).clk.eq(self.gtps[i].cd_rtio_rx.clk),
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getattr(self, "cd_rtio_rx" + str(i)).rst.eq(self.gtps[i].cd_rtio_rx.rst)
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]
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