mirror of https://github.com/m-labs/artiq.git
122 lines
4.4 KiB
Python
Executable File
122 lines
4.4 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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import os
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from migen import *
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from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.cores import gpio
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.builder import *
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from misoc.targets.sayma_amc import BaseSoC
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from microscope import *
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio import DRTIOSatellite
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from artiq import __version__ as artiq_version
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from artiq import __artiq_dir__ as artiq_dir
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class Satellite(BaseSoC):
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mem_map = {
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"drtio_aux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules += Microscope(platform.request("serial", 1),
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self.clk_freq)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
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self.submodules.transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.transceiver.channels[0], rtio_channels))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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i_I=ClockSignal("rtio_rx0"),
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder / Sayma DRTIO satellite")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = Satellite(**soc_sdram_argdict(args))
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firmware_dir = os.path.join(artiq_dir, "firmware")
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builder = Builder(soc, **builder_argdict(args))
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builder.software_packages = []
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builder.add_software_package("bootloader", os.path.join(firmware_dir, "bootloader"))
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builder.add_software_package("satman", os.path.join(firmware_dir, "satman"))
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builder.build()
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if __name__ == "__main__":
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main()
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