From 4fa202867167445b2ad94a93c73334e9b6220b66 Mon Sep 17 00:00:00 2001 From: Marius Weber Date: Tue, 6 Apr 2021 17:34:28 +0100 Subject: [PATCH] phaser: fix coarse mixer register offset The CMIX bits are bits 12-15 in register 0x0d. This has been checked against the datasheet and verified on hardware. Until now, the bit for CMIX1 was written to CMIX0. The CMIX0 bit was written to a reserved bit. Signed-off-by: Marius Weber --- artiq/coredevice/dac34h84.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/coredevice/dac34h84.py b/artiq/coredevice/dac34h84.py index 51b93e6a0..4063551aa 100644 --- a/artiq/coredevice/dac34h84.py +++ b/artiq/coredevice/dac34h84.py @@ -201,7 +201,7 @@ class DAC34H84: mmap.append( (0x0d << 16) | (self.cmix_fs8 << 15) | (self.cmix_fs4 << 14) | - (self.cmix_fs2 << 12) | (self.cmix_nfs4 << 11) | + (self.cmix_fs2 << 13) | (self.cmix_nfs4 << 12) | (self.qmc_gainb << 0)) mmap.append((0x0e << 16) | (self.qmc_gainc << 0)) mmap.append(