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VLBAI{Master,Slave}: align rtio channels with PTB

This commit is contained in:
Robert Jördens 2018-09-04 10:39:45 +00:00
parent c55460f59f
commit 47eb37e212
1 changed files with 12 additions and 8 deletions
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12
artiq/gateware/targets/kasli.py
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@ -908,12 +908,14 @@ class VLBAIMaster(_MasterBase):
eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
phy = ttl_simple.Output(self.platform.request("user_led", 0))
for i in (0, 1):
phy = ttl_simple.Output(self.platform.request("user_led", i))
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel())
@ -938,12 +940,14 @@ class VLBAISatellite(_SatelliteBase):
eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
phy = ttl_simple.Output(self.platform.request("user_led", 0))
for i in (0, 1):
phy = ttl_simple.Output(self.platform.request("user_led", i))
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))
eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
self.add_rtio(self.rtio_channels)