From 47eb37e2125552b779d6e0a3e25076c3924446c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Tue, 4 Sep 2018 10:39:45 +0000 Subject: [PATCH] VLBAI{Master,Slave}: align rtio channels with PTB --- artiq/gateware/targets/kasli.py | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index b9759a99e..ef1fa64f7 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -908,11 +908,13 @@ class VLBAIMaster(_MasterBase): eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X) - eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) - phy = ttl_simple.Output(self.platform.request("user_led", 0)) - self.submodules += phy - self.rtio_channels.append(rtio.Channel.from_phy(phy)) + for i in (0, 1): + phy = ttl_simple.Output(self.platform.request("user_led", i)) + self.submodules += phy + self.rtio_channels.append(rtio.Channel.from_phy(phy)) + + eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) @@ -938,11 +940,13 @@ class VLBAISatellite(_SatelliteBase): eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X) eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X) - eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) - phy = ttl_simple.Output(self.platform.request("user_led", 0)) - self.submodules += phy - self.rtio_channels.append(rtio.Channel.from_phy(phy)) + for i in (0, 1): + phy = ttl_simple.Output(self.platform.request("user_led", i)) + self.submodules += phy + self.rtio_channels.append(rtio.Channel.from_phy(phy)) + + eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X) self.add_rtio(self.rtio_channels)