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rtio/dma: fix previous commit

This commit is contained in:
Sebastien Bourdeauducq 2020-07-12 10:14:22 +08:00
parent f2e0d27334
commit 4340a5cfc1
1 changed files with 1 additions and 1 deletions
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artiq/gateware/rtio/dma.py
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@ -12,7 +12,7 @@ def _reverse_bytes(s, g):
class WishboneReader(Module): class WishboneReader(Module):
def __init__(self): def __init__(self, bus):
self.bus = bus self.bus = bus
aw = len(bus.adr) aw = len(bus.adr)