diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py
index dd1e23f55..20d558672 100644
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@@ -12,7 +12,7 @@ def _reverse_bytes(s, g):
 
 
 class WishboneReader(Module):
-    def __init__(self):
+    def __init__(self, bus):
         self.bus = bus
 
         aw = len(bus.adr)