From 28211e0b32f92e73a650364f129ce4cc9ba7aac2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 31 Mar 2017 15:35:28 +0800 Subject: [PATCH] gateware: reset RTIO DMA core when kernel CPU is reset --- artiq/gateware/targets/kc705_dds.py | 3 ++- artiq/gateware/targets/kc705_drtio_master.py | 3 ++- artiq/gateware/targets/phaser.py | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py index 4ecb108e1..32a1d1e3f 100755 --- a/artiq/gateware/targets/kc705_dds.py +++ b/artiq/gateware/targets/kc705_dds.py @@ -144,7 +144,8 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.submodules.rtio_core = rtio.Core(rtio_channels) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() - self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if()) + self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( + rtio.DMA(self.get_native_sdram_if())) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index 150676460..f41e2fafc 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -107,7 +107,8 @@ class Master(MiniSoC, AMPSoC): self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() - self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if()) + self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( + rtio.DMA(self.get_native_sdram_if())) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index 56d6fdaa5..d357ff04b 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -233,7 +233,8 @@ class Phaser(MiniSoC, AMPSoC): self.submodules.rtio_core = rtio.Core(rtio_channels) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() - # self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if()) + # self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( + # rtio.DMA(self.get_native_sdram_if())) self.register_kernel_cpu_csrdevice("rtio") # self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared(