diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py
index 4ecb108e1..32a1d1e3f 100755
--- a/artiq/gateware/targets/kc705_dds.py
+++ b/artiq/gateware/targets/kc705_dds.py
@@ -144,7 +144,8 @@ class _NIST_Ions(MiniSoC, AMPSoC):
         self.submodules.rtio_core = rtio.Core(rtio_channels)
         self.csr_devices.append("rtio_core")
         self.submodules.rtio = rtio.KernelInitiator()
-        self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
+        self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
+            rtio.DMA(self.get_native_sdram_if()))
         self.register_kernel_cpu_csrdevice("rtio")
         self.register_kernel_cpu_csrdevice("rtio_dma")
         self.submodules.cri_con = rtio.CRIInterconnectShared(
diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py
index 150676460..f41e2fafc 100755
--- a/artiq/gateware/targets/kc705_drtio_master.py
+++ b/artiq/gateware/targets/kc705_drtio_master.py
@@ -107,7 +107,8 @@ class Master(MiniSoC, AMPSoC):
         self.csr_devices.append("rtio_core")
 
         self.submodules.rtio = rtio.KernelInitiator()
-        self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
+        self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
+            rtio.DMA(self.get_native_sdram_if()))
         self.register_kernel_cpu_csrdevice("rtio")
         self.register_kernel_cpu_csrdevice("rtio_dma")
         self.submodules.cri_con = rtio.CRIInterconnectShared(
diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py
index 56d6fdaa5..d357ff04b 100755
--- a/artiq/gateware/targets/phaser.py
+++ b/artiq/gateware/targets/phaser.py
@@ -233,7 +233,8 @@ class Phaser(MiniSoC, AMPSoC):
         self.submodules.rtio_core = rtio.Core(rtio_channels)
         self.csr_devices.append("rtio_core")
         self.submodules.rtio = rtio.KernelInitiator()
-        # self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
+        # self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
+        #     rtio.DMA(self.get_native_sdram_if()))
         self.register_kernel_cpu_csrdevice("rtio")
         # self.register_kernel_cpu_csrdevice("rtio_dma")
         self.submodules.cri_con = rtio.CRIInterconnectShared(