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targets: default to vexriscv cpu

This commit is contained in:
occheung 2021-08-16 15:42:58 +08:00
parent be5ae5c5b4
commit 1b516b16e2
5 changed files with 9 additions and 9 deletions
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6
artiq/gateware/targets/kasli.py
View File

@ -116,7 +116,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
def __init__(self, gateware_identifier_str=None, **kwargs): def __init__(self, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
integrated_sram_size=8192, integrated_sram_size=8192,
@ -298,7 +298,7 @@ class MasterBase(MiniSoC, AMPSoC):
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, **kwargs): def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
integrated_sram_size=8192, integrated_sram_size=8192,
@ -474,7 +474,7 @@ class SatelliteBase(BaseSoC):
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs): def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs):
BaseSoC.__init__(self, BaseSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
**kwargs) **kwargs)

6
artiq/gateware/targets/kc705.py
View File

@ -172,7 +172,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
def __init__(self, gateware_identifier_str=None, **kwargs): def __init__(self, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
integrated_sram_size=8192, integrated_sram_size=8192,
@ -249,7 +249,7 @@ class _MasterBase(MiniSoC, AMPSoC):
def __init__(self, gateware_identifier_str=None, **kwargs): def __init__(self, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
integrated_sram_size=8192, integrated_sram_size=8192,
@ -382,7 +382,7 @@ class _SatelliteBase(BaseSoC):
def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs): def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs):
BaseSoC.__init__(self, BaseSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
integrated_sram_size=8192, integrated_sram_size=8192,

2
artiq/gateware/targets/metlino.py
View File

@ -42,7 +42,7 @@ class Master(MiniSoC, AMPSoC):
def __init__(self, gateware_identifier_str=None, **kwargs): def __init__(self, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
integrated_sram_size=8192, integrated_sram_size=8192,

2
artiq/gateware/targets/sayma_amc.py
View File

@ -56,7 +56,7 @@ class SatelliteBase(MiniSoC):
def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs): def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
integrated_sram_size=8192, integrated_sram_size=8192,

2
artiq/gateware/targets/sayma_rtm.py
View File

@ -77,7 +77,7 @@ class _SatelliteBase(BaseSoC):
def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs): def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs):
BaseSoC.__init__(self, BaseSoC.__init__(self,
cpu_type="or1k", cpu_type="vexriscv",
**kwargs) **kwargs)
add_identifier(self, gateware_identifier_str=gateware_identifier_str) add_identifier(self, gateware_identifier_str=gateware_identifier_str)
self.rtio_clk_freq = rtio_clk_freq self.rtio_clk_freq = rtio_clk_freq