From 1b516b16e266e2a22f3387adefe41906f3066e55 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Mon, 16 Aug 2021 15:42:58 +0800
Subject: [PATCH] targets: default to vexriscv cpu

---
 artiq/gateware/targets/kasli.py     | 6 +++---
 artiq/gateware/targets/kc705.py     | 6 +++---
 artiq/gateware/targets/metlino.py   | 2 +-
 artiq/gateware/targets/sayma_amc.py | 2 +-
 artiq/gateware/targets/sayma_rtm.py | 2 +-
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index 91c6fb9a0..131d75a79 100755
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -116,7 +116,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
 
     def __init__(self, gateware_identifier_str=None, **kwargs):
         MiniSoC.__init__(self,
-                         cpu_type="or1k",
+                         cpu_type="vexriscv",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          integrated_sram_size=8192,
@@ -298,7 +298,7 @@ class MasterBase(MiniSoC, AMPSoC):
 
     def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, **kwargs):
         MiniSoC.__init__(self,
-                         cpu_type="or1k",
+                         cpu_type="vexriscv",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          integrated_sram_size=8192,
@@ -474,7 +474,7 @@ class SatelliteBase(BaseSoC):
 
     def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs):
         BaseSoC.__init__(self,
-                 cpu_type="or1k",
+                 cpu_type="vexriscv",
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
                  **kwargs)
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 9d167b566..0b69c18b1 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -172,7 +172,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
 
     def __init__(self, gateware_identifier_str=None, **kwargs):
         MiniSoC.__init__(self,
-                         cpu_type="or1k",
+                         cpu_type="vexriscv",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          integrated_sram_size=8192,
@@ -249,7 +249,7 @@ class _MasterBase(MiniSoC, AMPSoC):
 
     def __init__(self, gateware_identifier_str=None, **kwargs):
         MiniSoC.__init__(self,
-                         cpu_type="or1k",
+                         cpu_type="vexriscv",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          integrated_sram_size=8192,
@@ -382,7 +382,7 @@ class _SatelliteBase(BaseSoC):
 
     def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs):
         BaseSoC.__init__(self,
-                 cpu_type="or1k",
+                 cpu_type="vexriscv",
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
                  integrated_sram_size=8192,
diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py
index 4f609e1c7..74c2e35f0 100755
--- a/artiq/gateware/targets/metlino.py
+++ b/artiq/gateware/targets/metlino.py
@@ -42,7 +42,7 @@ class Master(MiniSoC, AMPSoC):
 
     def __init__(self, gateware_identifier_str=None, **kwargs):
         MiniSoC.__init__(self,
-                         cpu_type="or1k",
+                         cpu_type="vexriscv",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          integrated_sram_size=8192,
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index f46942e67..6155eb31f 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -56,7 +56,7 @@ class SatelliteBase(MiniSoC):
 
     def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs):
         MiniSoC.__init__(self,
-                 cpu_type="or1k",
+                 cpu_type="vexriscv",
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
                  integrated_sram_size=8192,
diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index 294a17823..a302a795f 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -77,7 +77,7 @@ class _SatelliteBase(BaseSoC):
 
     def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs):
         BaseSoC.__init__(self,
-                 cpu_type="or1k",
+                 cpu_type="vexriscv",
                  **kwargs)
         add_identifier(self, gateware_identifier_str=gateware_identifier_str)
         self.rtio_clk_freq = rtio_clk_freq