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coredevice/TTLClockGen: fix attribute init

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Sebastien Bourdeauducq 2015-08-27 09:48:11 +08:00
parent 4cb0d4589e
commit 1991b3c910
1 changed files with 0 additions and 1 deletions
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artiq/coredevice/ttl.py
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@ -220,7 +220,6 @@ class TTLClockGen:
self.core = dmgr.get("core")
self.channel = channel
def build(self):
# in RTIO cycles
self.previous_timestamp = int64(0)
self.acc_width = 24