From 1991b3c91051b204d140c99e278a2eec05dca38d Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 27 Aug 2015 09:48:11 +0800
Subject: [PATCH] coredevice/TTLClockGen: fix attribute init

---
 artiq/coredevice/ttl.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py
index d54710e66..6285678af 100644
--- a/artiq/coredevice/ttl.py
+++ b/artiq/coredevice/ttl.py
@@ -220,7 +220,6 @@ class TTLClockGen:
         self.core = dmgr.get("core")
         self.channel = channel
 
-    def build(self):
         # in RTIO cycles
         self.previous_timestamp = int64(0)
         self.acc_width = 24