diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py
index d54710e66..6285678af 100644
--- a/artiq/coredevice/ttl.py
+++ b/artiq/coredevice/ttl.py
@@ -220,7 +220,6 @@ class TTLClockGen:
         self.core = dmgr.get("core")
         self.channel = channel
 
-    def build(self):
         # in RTIO cycles
         self.previous_timestamp = int64(0)
         self.acc_width = 24