M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

coredevice/TTLClockGen: fix attribute init

This commit is contained in:
Sebastien Bourdeauducq 2015-08-27 09:48:11 +08:00
parent 4cb0d4589e
commit 1991b3c910
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/coredevice/ttl.py
View File

@ -220,7 +220,6 @@ class TTLClockGen:
self.core = dmgr.get("core") self.core = dmgr.get("core")
self.channel = channel self.channel = channel
def build(self):
# in RTIO cycles # in RTIO cycles
self.previous_timestamp = int64(0) self.previous_timestamp = int64(0)
self.acc_width = 24 self.acc_width = 24