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coredevice/TTLClockGen: fix attribute init
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@ -220,7 +220,6 @@ class TTLClockGen:
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self.core = dmgr.get("core")
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self.core = dmgr.get("core")
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self.channel = channel
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self.channel = channel
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def build(self):
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# in RTIO cycles
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# in RTIO cycles
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self.previous_timestamp = int64(0)
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self.previous_timestamp = int64(0)
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self.acc_width = 24
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self.acc_width = 24
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