2014-07-25 13:50:20 +08:00
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from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg
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2014-07-26 06:23:35 +08:00
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from artiqlib.rtio.rbus import create_rbus
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2014-07-25 13:50:20 +08:00
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2014-09-05 12:03:22 +08:00
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2014-07-26 06:23:35 +08:00
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class SimplePHY(Module):
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2014-11-30 00:13:54 +08:00
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def __init__(self, pads, output_only_pads=set()):
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self.rbus = create_rbus(0, pads, output_only_pads)
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2014-09-05 12:03:22 +08:00
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self.loopback_latency = 3
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2014-07-25 13:50:20 +08:00
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2014-09-05 12:03:22 +08:00
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# # #
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2014-07-26 06:23:35 +08:00
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2014-09-05 12:03:22 +08:00
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for pad, chif in zip(pads, self.rbus):
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o_pad = Signal()
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2014-11-30 00:13:54 +08:00
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self.sync.rio += If(chif.o_stb, o_pad.eq(chif.o_value))
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2014-09-11 23:09:43 +08:00
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if hasattr(chif, "oe"):
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2014-09-05 12:03:22 +08:00
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ts = TSTriple()
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i_pad = Signal()
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2014-11-30 00:13:54 +08:00
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self.sync.rio += ts.oe.eq(chif.oe)
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2014-09-05 12:03:22 +08:00
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self.comb += ts.o.eq(o_pad)
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2014-11-30 10:50:48 +08:00
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self.specials += MultiReg(ts.i, i_pad, "rio"), \
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2014-09-05 12:03:22 +08:00
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ts.get_tristate(pad)
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2014-07-25 13:50:20 +08:00
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2014-09-05 12:03:22 +08:00
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i_pad_d = Signal()
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2014-11-30 00:13:54 +08:00
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self.sync.rio += i_pad_d.eq(i_pad)
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2014-09-05 12:03:22 +08:00
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self.comb += chif.i_stb.eq(i_pad ^ i_pad_d), \
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chif.i_value.eq(i_pad)
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2014-09-11 23:09:43 +08:00
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else:
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self.comb += pad.eq(o_pad)
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