mirror of https://github.com/m-labs/artiq.git
soc/rtio: input support
This commit is contained in:
parent
6b6b44b924
commit
9e4bc35354
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@ -1,111 +1,2 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered
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from migen.genlib.cdc import MultiReg
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from types import SimpleNamespace
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from artiqlib.rtio import phy
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class RTIOBankO(Module):
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def __init__(self, channels, counter_width, fine_ts_width, fifo_depth):
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self.sel = Signal(max=len(channels))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal()
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self.writable = Signal()
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self.we = Signal()
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self.underflow = Signal()
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self.level = Signal(bits_for(fifo_depth))
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###
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counter = Signal(counter_width)
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self.sync += [
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counter.eq(counter + 1),
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If(self.we & self.writable,
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If(self.timestamp[fine_ts_width:] < counter + 2, self.underflow.eq(1))
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)
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]
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fifos = []
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for n, channel in enumerate(channels):
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fifo = SyncFIFOBuffered([
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("timestamp", counter_width+fine_ts_width), ("value", 2)],
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fifo_depth)
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self.submodules += fifo
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fifos.append(fifo)
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# FIFO write
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self.comb += [
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fifo.din.timestamp.eq(self.timestamp),
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fifo.din.value.eq(self.value),
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fifo.we.eq(self.we & (self.sel == n))
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]
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# FIFO read
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self.comb += [
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channel.hit.eq(fifo.readable &
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(fifo.dout.timestamp[fine_ts_width:] == counter)),
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channel.value.eq(fifo.dout.value),
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fifo.re.eq(channel.hit)
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]
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if fine_ts_width:
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self.comb += channel.fine_ts.eq(fifo.dout.timestamp[:fine_ts_width])
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selfifo = Array(fifos)[self.sel]
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self.comb += self.writable.eq(selfifo.writable), self.level.eq(selfifo.level)
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class RTIO(Module, AutoCSR):
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def __init__(self, phy, counter_width=32, ofifo_depth=8, ififo_depth=8):
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# Extract info from PHY
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if hasattr(phy.interface[0], "o_fine_ts"):
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fine_ts_width = flen(channels[0].o_fine_ts)
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else:
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fine_ts_width = 0
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oes = [padif.oe for padif in phy.interface if hasattr(padif, "oe")]
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# Submodules
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self.submodules.bank_o = InsertReset(RTIOBankO(
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[SimpleNamespace(hit=padif.o_set_value,
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value=padif.o_value,
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fine_ts=getattr(padif, "o_fine_ts", None))
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for padif in phy.interface],
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counter_width, fine_ts_width, ofifo_depth))
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# CSRs
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_oe = CSR()
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self._r_o_timestamp = CSRStorage(counter_width+fine_ts_width)
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self._r_o_value = CSRStorage()
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_underflow = CSRStatus()
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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# OE
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oes = []
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for n, padif in enumerate(phy.interface):
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if hasattr(padif, "oe"):
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self.sync += \
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If(self._r_oe.re & (self._r_chan_sel.storage == n),
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padif.oe.eq(self._r_oe.r)
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)
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oes.append(padif.oe)
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else:
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oes.append(1)
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self.comb += self._r_oe.w.eq(Array(oes)[self._r_chan_sel.storage])
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# Output/Gate
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self.comb += [
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self.bank_o.reset.eq(self._r_reset.storage),
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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self.bank_o.timestamp.eq(self._r_o_timestamp.storage),
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self.bank_o.value.eq(self._r_o_value.storage),
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self._r_o_writable.status.eq(self.bank_o.writable),
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self.bank_o.we.eq(self._r_o_we.re),
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self._r_o_underflow.status.eq(self.bank_o.underflow),
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self._r_o_level.status.eq(self.bank_o.level)
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]
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from artiqlib.rtio.core import RTIO
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@ -0,0 +1,183 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered
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from migen.genlib.cdc import MultiReg
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from artiqlib.rtio.rbus import get_fine_ts_width
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class _RTIOBankO(Module):
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def __init__(self, rbus, counter_width, fine_ts_width, fifo_depth, counter_init):
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal(2)
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self.writable = Signal()
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self.we = Signal()
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self.underflow = Signal()
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self.level = Signal(bits_for(fifo_depth))
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###
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counter = Signal(counter_width, reset=counter_init)
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self.sync += [
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counter.eq(counter + 1),
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If(self.we & self.writable,
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If(self.timestamp[fine_ts_width:] < counter + 2, self.underflow.eq(1))
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)
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]
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fifos = []
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for n, chif in enumerate(rbus):
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fifo = SyncFIFOBuffered([
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("timestamp", counter_width+fine_ts_width), ("value", 2)],
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fifo_depth)
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self.submodules += fifo
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fifos.append(fifo)
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# FIFO write
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self.comb += [
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fifo.din.timestamp.eq(self.timestamp),
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fifo.din.value.eq(self.value),
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fifo.we.eq(self.we & (self.sel == n))
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]
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# FIFO read
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self.comb += [
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chif.o_stb.eq(fifo.readable &
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(fifo.dout.timestamp[fine_ts_width:] == counter)),
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chif.o_value.eq(fifo.dout.value),
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fifo.re.eq(chif.o_stb)
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]
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if fine_ts_width:
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self.comb += chif.o_fine_ts.eq(fifo.dout.timestamp[:fine_ts_width])
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selfifo = Array(fifos)[self.sel]
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self.comb += self.writable.eq(selfifo.writable), self.level.eq(selfifo.level)
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class _RTIOBankI(Module):
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def __init__(self, rbus, counter_width, fine_ts_width, fifo_depth):
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal()
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self.readable = Signal()
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self.re = Signal()
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self.overflow = Signal()
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###
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counter = Signal(counter_width)
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self.sync += counter.eq(counter + 1)
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timestamps = []
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values = []
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readables = []
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overflows = []
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for n, chif in enumerate(rbus):
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if hasattr(chif, "oe"):
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sensitivity = Signal(2)
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self.sync += If(~chif.oe & chif.o_stb,
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sensitivity.eq(chif.o_value))
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fifo = SyncFIFOBuffered([
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("timestamp", counter_width+fine_ts_width), ("value", 1)],
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fifo_depth)
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self.submodules += fifo
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# FIFO write
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if fine_ts_width:
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full_ts = Cat(chif.i_fine_ts, counter)
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else:
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full_ts = counter
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self.comb += [
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fifo.din.timestamp.eq(full_ts),
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fifo.din.value.eq(chif.i_value),
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fifo.we.eq(~chif.oe & chif.i_stb &
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((chif.i_value & sensitivity[0]) | (~chif.i_value & sensitivity[1])))
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]
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# FIFO read
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timestamps.append(fifo.dout.timestamp)
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values.append(fifo.dout.value)
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readables.append(fifo.readable)
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self.comb += fifo.re.eq(self.re & (self.sel == n))
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overflow = Signal()
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self.sync += If(fifo.we & ~fifo.writable, overflow.eq(1))
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overflows.append(overflow)
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else:
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timestamps.append(0)
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values.append(0)
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readables.append(0)
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overflows.append(0)
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self.comb += [
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self.timestamp.eq(Array(timestamps)[self.sel]),
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self.value.eq(Array(values)[self.sel]),
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self.readable.eq(Array(readables)[self.sel]),
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self.overflow.eq(Array(overflows)[self.sel])
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]
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class RTIO(Module, AutoCSR):
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def __init__(self, phy, counter_width=32, ofifo_depth=8, ififo_depth=8):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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# Submodules
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self.submodules.bank_o = InsertReset(_RTIOBankO(phy.rbus,
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counter_width, fine_ts_width, ofifo_depth,
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phy.loopback_latency))
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self.submodules.bank_i = InsertReset(_RTIOBankI(phy.rbus,
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counter_width, fine_ts_width, ofifo_depth))
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# CSRs
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_oe = CSR()
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self._r_o_timestamp = CSRStorage(counter_width+fine_ts_width)
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self._r_o_value = CSRStorage(2)
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_underflow = CSRStatus()
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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self._r_i_timestamp = CSRStatus(counter_width+fine_ts_width)
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self._r_i_value = CSRStatus()
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self._r_i_readable = CSRStatus()
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self._r_i_re = CSR()
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self._r_i_overflow = CSRStatus()
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# OE
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oes = []
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for n, chif in enumerate(phy.rbus):
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if hasattr(chif, "oe"):
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self.sync += \
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If(self._r_oe.re & (self._r_chan_sel.storage == n),
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chif.oe.eq(self._r_oe.r)
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)
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oes.append(chif.oe)
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else:
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oes.append(1)
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self.comb += self._r_oe.w.eq(Array(oes)[self._r_chan_sel.storage])
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# Output/Gate
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self.comb += [
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self.bank_o.reset.eq(self._r_reset.storage),
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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self.bank_o.timestamp.eq(self._r_o_timestamp.storage),
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self.bank_o.value.eq(self._r_o_value.storage),
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self._r_o_writable.status.eq(self.bank_o.writable),
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self.bank_o.we.eq(self._r_o_we.re),
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self._r_o_underflow.status.eq(self.bank_o.underflow),
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self._r_o_level.status.eq(self.bank_o.level)
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]
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# Input
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self.comb += [
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self.bank_i.reset.eq(self._r_reset.storage),
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self.bank_i.sel.eq(self._r_chan_sel.storage),
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self._r_i_timestamp.status.eq(self.bank_i.timestamp),
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self._r_i_value.status.eq(self.bank_i.value),
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self._r_i_readable.status.eq(self.bank_i.readable),
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self.bank_i.re.eq(self._r_i_re.re),
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self._r_i_overflow.status.eq(self.bank_i.overflow)
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]
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@ -1,50 +1,29 @@
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from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.record import Record
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class PHYBase(Module):
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def __init__(self, fine_ts_bits, pads, output_only_pads):
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self.interface = []
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for pad in pads:
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layout = [
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("o_set_value", 1),
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("o_value", 1)
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]
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if fine_ts_bits:
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layout.append(("o_fine_ts", fine_ts_bits))
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if pad not in output_only_pads:
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layout += [
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("oe", 1),
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("i_detect", 1),
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("i_value", 1)
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]
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if fine_ts_bits:
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layout.append(("i_fine_ts", fine_ts_bits))
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self.interface.append(Record(layout))
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from artiqlib.rtio.rbus import create_rbus
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class SimplePHY(PHYBase):
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class SimplePHY(Module):
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def __init__(self, pads, output_only_pads=set()):
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PHYBase.__init__(self, 0, pads, output_only_pads)
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self.rbus = create_rbus(0, pads, output_only_pads)
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self.loopback_latency = 3
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for pad, padif in zip(pads, self.interface):
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o_pad_d1 = Signal()
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###
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for pad, chif in zip(pads, self.rbus):
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o_pad = Signal()
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self.sync += [
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If(padif.o_set_value, o_pad_d1.eq(padif.o_value)),
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o_pad.eq(o_pad_d1)
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]
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self.sync += If(chif.o_stb, o_pad.eq(chif.o_value))
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if pad in output_only_pads:
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self.comb += pad.eq(o_pad)
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else:
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ts = TSTriple()
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i_pad = Signal()
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self.sync += ts.oe.eq(padif.oe)
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self.sync += ts.oe.eq(chif.oe)
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self.comb += ts.o.eq(o_pad)
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self.specials += MultiReg(ts.i, i_pad), \
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ts.get_tristate(pad)
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i_pad_d = Signal()
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self.sync += i_pad_d.eq(i_pad)
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self.comb += padif.i_detect.eq(i_pad ^ i_pad_d), \
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padif.i_value.eq(i_pad)
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self.comb += chif.i_stb.eq(i_pad ^ i_pad_d), \
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chif.i_value.eq(i_pad)
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@ -0,0 +1,28 @@
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from migen.fhdl.std import *
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from migen.genlib.record import Record
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def create_rbus(fine_ts_bits, pads, output_only_pads):
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rbus = []
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for pad in pads:
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layout = [
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("o_stb", 1),
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("o_value", 2)
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]
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if fine_ts_bits:
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layout.append(("o_fine_ts", fine_ts_bits))
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if pad not in output_only_pads:
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layout += [
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("oe", 1),
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("i_stb", 1),
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("i_value", 1)
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]
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if fine_ts_bits:
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layout.append(("i_fine_ts", fine_ts_bits))
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rbus.append(Record(layout))
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return rbus
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def get_fine_ts_width(rbus):
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if hasattr(rbus[0], "o_fine_ts"):
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return flen(rbus[0].o_fine_ts)
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else:
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return 0
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