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WRPLL runtime: reduce output jitter of mmcm #294

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sb10q merged 2 commits from morgan/artiq-zynq:wrpll_mmcm_fix into master 2024-04-29 11:20:50 +08:00
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src/gateware/wrpll.py
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@ -203,7 +203,7 @@ class SMAFrequencyMultiplier(Module, AutoCSR):
# MMCME2 is capable to accept 10MHz input while PLLE2 only support down to 19MHz input (DS191)
# The MMCME2 can be reconfiged during runtime using the Dynamic Reconfiguration Ports
Instance("MMCME2_ADV",
p_BANDWIDTH="LOW", # lower jitter
p_BANDWIDTH="HIGH", # lower output jitter (see https://support.xilinx.com/s/question/0D52E00006iHqRqSAK)
o_LOCKED=self.mmcm_locked.status,
i_RST=self.mmcm_reset.storage,