diff --git a/src/gateware/wrpll.py b/src/gateware/wrpll.py
index a6b2b48..aaf604b 100644
--- a/src/gateware/wrpll.py
+++ b/src/gateware/wrpll.py
@@ -203,7 +203,7 @@ class SMAFrequencyMultiplier(Module, AutoCSR):
             # MMCME2 is capable to accept 10MHz input while PLLE2 only support down to 19MHz input (DS191)
             # The MMCME2 can be reconfiged during runtime using the Dynamic Reconfiguration Ports
             Instance("MMCME2_ADV",
-                p_BANDWIDTH="LOW",  # lower jitter
+                p_BANDWIDTH="HIGH",  # lower output jitter (see https://support.xilinx.com/s/question/0D52E00006iHqRqSAK)
                 o_LOCKED=self.mmcm_locked.status,
                 i_RST=self.mmcm_reset.storage,
                 
diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs
index fc906c1..06918b2 100644
--- a/src/runtime/src/rtio_clocking.rs
+++ b/src/runtime/src/rtio_clocking.rs
@@ -278,8 +278,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
                 lock_reg2: 0x7c01,
                 lock_reg3: 0xffe9,
                 power_reg: 0x9900,
-                filt_reg1: 0x0808,
-                filt_reg2: 0x0800,
+                filt_reg1: 0x1008,
+                filt_reg2: 0x8800,
             },
             false,
         ),
@@ -295,8 +295,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
                 lock_reg2: 0x7c01,
                 lock_reg3: 0xffe9,
                 power_reg: 0x9900,
-                filt_reg1: 0x0808,
-                filt_reg2: 0x9800,
+                filt_reg1: 0x9908,
+                filt_reg2: 0x8100,
             },
             false,
         ),
@@ -312,8 +312,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
                 lock_reg2: 0x7c01,
                 lock_reg3: 0xffe9,
                 power_reg: 0x9900,
-                filt_reg1: 0x0808,
-                filt_reg2: 0x9800,
+                filt_reg1: 0x9108,
+                filt_reg2: 0x0100,
             },
             false,
         ),
@@ -329,7 +329,7 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
                 lock_reg2: 0x7001,
                 lock_reg3: 0xf3e9,
                 power_reg: 0x0100,
-                filt_reg1: 0x0808,
+                filt_reg1: 0x9908,
                 filt_reg2: 0x1100,
             },
             true,