WRPLL runtime: reduce output jitter of mmcm #294

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sb10q merged 2 commits from morgan/artiq-zynq:wrpll_mmcm_fix into master 2024-04-29 11:20:50 +08:00
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Summary

Phase noise measurement

  • SynthNV 100MHz <-> Standalone @ 125MHz
    mmcm_fix
## Summary - around 8dB "knee" improvement for 10MHz, 80Mhz, 100Mhz SMACLKin options - firmware - update the DRP config with `p_BANDWIDTH="HIGH"` for better output jitter performance (see https://support.xilinx.com/s/question/0D52E00006iHqRqSAK) - gateware - set `p_BANDWIDTH="HIGH"` and update docs ## Phase noise measurement - SynthNV 100MHz <-> Standalone @ 125MHz ![mmcm_fix](/attachments/a71b0bbf-3ba4-4614-8b81-54dead67c6ab)
morgan added 2 commits 2024-04-26 17:07:31 +08:00
sb10q merged commit cca23aa2a5 into master 2024-04-29 11:20:50 +08:00
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Reference: M-Labs/artiq-zynq#294
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