RTIO/SYS Clock merge #212

Merged
sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
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@ -68,30 +68,11 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) { fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
#[cfg(has_rtio_crg_clock_sel)]
let clock_sel = match _clk {
RtioClock::Ext0_Bypass => {
info!("Using bypassed external clock");
1
},
RtioClock::Int_125 => {
info!("Using internal RTIO clock");
0
},
_ => {
warn!("rtio_clock setting '{:?}' is not supported. Using default internal RTIO clock instead", _clk);
0
}
};
unsafe { unsafe {
pl::csr::rtio_crg::pll_reset_write(1); pl::csr::sys_crg::pll_reset_write(0);
#[cfg(has_rtio_crg_clock_sel)]
pl::csr::rtio_crg::clock_sel_write(clock_sel);
pl::csr::rtio_crg::pll_reset_write(0);
} }
timer.delay_ms(1); timer.delay_ms(1);
let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 }; let locked = unsafe { pl::csr::sys_crg::pll_locked_read() != 0 };
if locked { if locked {
info!("RTIO PLL locked"); info!("RTIO PLL locked");
} else { } else {