From e9d5c41c3d36a5143f03b54f3b5468ba55e91d32 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 6 Jan 2023 16:41:25 +0800 Subject: [PATCH 01/30] kasli_soc: merge sys/rtio on standalone --- src/gateware/kasli_soc.py | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 36dfad9..6060656 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -26,12 +26,12 @@ import analyzer import acpki import drtio_aux_controller -class RTIOCRG(Module, AutoCSR): +class SYSCRG(Module, AutoCSR): def __init__(self, platform): self.pll_reset = CSRStorage(reset=1) self.pll_locked = CSRStatus() - self.clock_domains.cd_rtio = ClockDomain() - self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) clk_synth = platform.request("cdr_clk_clean_fabric") clk_synth_se = Signal() @@ -43,8 +43,8 @@ class RTIOCRG(Module, AutoCSR): ] pll_locked = Signal() - rtio_clk = Signal() - rtiox4_clk = Signal() + sys_clk = Signal() + sys4x_clk = Signal() fb_clk = Signal() self.specials += [ Instance("PLLE2_ADV", @@ -64,16 +64,16 @@ class RTIOCRG(Module, AutoCSR): o_CLKFBOUT=fb_clk, p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=rtiox4_clk, + o_CLKOUT0=sys4x_clk, p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=rtio_clk), - Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk), - Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk), + o_CLKOUT1=sys_clk), + Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_rtio, ~pll_locked), - MultiReg(pll_locked, self.pll_locked.status) + AsyncResetSynchronizer(self.cd_sys, ~pll_locked), ] + self.comb += self.pll_locked.status.eq(pll_locked) eem_iostandard_dict = { @@ -121,7 +121,7 @@ class GenericStandalone(SoCCore): ident = description["variant"] if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") @@ -132,12 +132,11 @@ class GenericStandalone(SoCCore): self.rustc_cfg["si5324_soft_reset"] = None self.crg = self.ps7 # HACK for eem_7series to find the clock - self.submodules.rtio_crg = RTIOCRG(self.platform) - self.csr_devices.append("rtio_crg") - self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) - self.platform.add_false_path_constraints( - self.ps7.cd_sys.clk, - self.rtio_crg.cd_rtio.clk) + self.submodules.sys_crg = SYSCRG(self.platform) + self.csr_devices.append("sys_crg") + # another hack since ps7 itself does not have cd_sys anymore + self.crg.cd_sys = self.sys_crg.cd_sys + self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) self.rtio_channels = [] has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) @@ -189,7 +188,7 @@ class GenericStandalone(SoCCore): self.add_csr_group("grabber", self.grabber_csr_group) for grabber in self.grabber_csr_group: self.platform.add_false_path_constraints( - self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk) + self.sys_crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk) class GenericMaster(SoCCore): -- 2.44.1 From b34f445e553cc61e45340f0c34ebd7c57420197a Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 6 Jan 2023 16:42:47 +0800 Subject: [PATCH 02/30] rtio_clocking: remove unnecessary rtio_crg code --- src/runtime/src/rtio_clocking.rs | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index de0f472..ffe513d 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -68,30 +68,11 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) { - #[cfg(has_rtio_crg_clock_sel)] - let clock_sel = match _clk { - RtioClock::Ext0_Bypass => { - info!("Using bypassed external clock"); - 1 - }, - RtioClock::Int_125 => { - info!("Using internal RTIO clock"); - 0 - }, - _ => { - warn!("rtio_clock setting '{:?}' is not supported. Using default internal RTIO clock instead", _clk); - 0 - } - }; - unsafe { - pl::csr::rtio_crg::pll_reset_write(1); - #[cfg(has_rtio_crg_clock_sel)] - pl::csr::rtio_crg::clock_sel_write(clock_sel); - pl::csr::rtio_crg::pll_reset_write(0); + pl::csr::sys_crg::pll_reset_write(0); } timer.delay_ms(1); - let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 }; + let locked = unsafe { pl::csr::sys_crg::pll_locked_read() != 0 }; if locked { info!("RTIO PLL locked"); } else { -- 2.44.1 From 5ab402139c16488b92bd67bd23c6017baedb49f8 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 11 Jan 2023 14:31:04 +0800 Subject: [PATCH 03/30] change init order, avoid providing bootstrap clock --- src/gateware/kasli_soc.py | 10 ++++------ src/runtime/src/main.rs | 6 +++--- src/runtime/src/rtio_clocking.rs | 7 ++----- 3 files changed, 9 insertions(+), 14 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 6060656..c7c9e1e 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -28,7 +28,6 @@ import drtio_aux_controller class SYSCRG(Module, AutoCSR): def __init__(self, platform): - self.pll_reset = CSRStorage(reset=1) self.pll_locked = CSRStatus() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -51,15 +50,14 @@ class SYSCRG(Module, AutoCSR): p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_BANDWIDTH="HIGH", p_REF_JITTER1=0.001, - p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0, - i_CLKIN2=clk_synth_se, - # Warning: CLKINSEL=0 means CLKIN2 is selected - i_CLKINSEL=0, + p_CLKIN1_PERIOD=8.0, + i_CLKIN1=clk_synth_se, + i_CLKINSEL=1, # VCO @ 1.5GHz when using 125MHz input p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, i_CLKFBIN=fb_clk, - i_RST=self.pll_reset.storage, + i_RST=0, o_CLKFBOUT=fb_clk, diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index a925be9..956a81d 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -111,9 +111,6 @@ pub fn main_core0() { ram::init_alloc_core0(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); - init_gateware(); - info!("gateware ident: {}", identifier_read(&mut [0; 64])); - i2c::init(); #[cfg(feature = "target_kasli_soc")] @@ -145,6 +142,9 @@ pub fn main_core0() { rtio_clocking::init(&mut timer, &cfg); + init_gateware(); + info!("gateware ident: {}", identifier_read(&mut [0; 64])); + task::spawn(report_async_rtio_errors()); comms::main(timer, cfg); diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index ffe513d..49a6c31 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -68,9 +68,6 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) { - unsafe { - pl::csr::sys_crg::pll_reset_write(0); - } timer.delay_ms(1); let locked = unsafe { pl::csr::sys_crg::pll_locked_read() != 0 }; if locked { @@ -230,9 +227,9 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) { _ => setup_si5324(i2c, timer, clk), } } - #[cfg(has_drtio)] - init_drtio(timer); init_rtio(timer, clk); + #[cfg(has_drtio)] + init_drtio(timer); } \ No newline at end of file -- 2.44.1 From 229cef0a07d04ab2648f902790169a7190145b7a Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 11 Jan 2023 14:32:26 +0800 Subject: [PATCH 04/30] zc706: change RTIO CRG to SYS --- src/gateware/zc706.py | 53 ++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 6bb7b4c..10a2039 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -27,48 +27,45 @@ import acpki import drtio_aux_controller -class RTIOCRG(Module, AutoCSR): - def __init__(self, platform, rtio_internal_clk): - self.clock_sel = CSRStorage() +class SYSCRG(Module, AutoCSR): + def __init__(self, platform): self.pll_reset = CSRStorage(reset=1) self.pll_locked = CSRStatus() - self.clock_domains.cd_rtio = ClockDomain() - self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) rtio_external_clk = Signal() - user_sma_clock = platform.request("user_sma_clock") - platform.add_period_constraint(user_sma_clock.p, 8.0) + si5324_out = platform.request("si5324_clkout") + platform.add_period_constraint(si5324_out.p, 8.0) self.specials += Instance("IBUFDS", - i_I=user_sma_clock.p, i_IB=user_sma_clock.n, + i_I=si5324_out.p, i_IB=si5324_out.n, o_O=rtio_external_clk) pll_locked = Signal() - rtio_clk = Signal() - rtiox4_clk = Signal() + sys_clk = Signal() + sys4x_clk = Signal() self.specials += [ Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_REF_JITTER1=0.01, - p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0, - i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk, - # Warning: CLKINSEL=0 means CLKIN2 is selected - i_CLKINSEL=~self.clock_sel.storage, + p_CLKIN1_PERIOD=8.0, + i_CLKIN1=rtio_external_clk, # VCO @ 1GHz when using 125MHz input p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, - i_CLKFBIN=self.cd_rtio.clk, + i_CLKFBIN=self.cd_sys.clk, i_RST=self.pll_reset.storage, - o_CLKFBOUT=rtio_clk, + o_CLKFBOUT=sys_clk, p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=rtiox4_clk), - Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk), - Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk), - AsyncResetSynchronizer(self.cd_rtio, ~pll_locked), - MultiReg(pll_locked, self.pll_locked.status) + o_CLKOUT0=sys4x_clk), + Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), + AsyncResetSynchronizer(self.cd_sys, ~pll_locked) ] + self.comb += self.pll_locked.status.eq(pll_locked) class SMAClkinForward(Module): @@ -150,15 +147,11 @@ class ZC706(SoCCore): ident = self.__class__.__name__ if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) - self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk) - self.csr_devices.append("rtio_crg") - self.rustc_cfg["has_rtio_crg_clock_sel"] = None - self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) - self.platform.add_false_path_constraints( - self.ps7.cd_sys.clk, - self.rtio_crg.cd_rtio.clk) + self.submodules.sys_crg = SYSCRG(self.platform) + self.csr_devices.append("sys_crg") + self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) def add_rtio(self, rtio_channels): self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) @@ -616,6 +609,7 @@ class _NIST_QC2_RTIO: class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): def __init__(self, acpki, drtio100mhz): ZC706.__init__(self, acpki) + self.submodules += SMAClkinForward(self.platform) _NIST_CLOCK_RTIO.__init__(self) class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO): @@ -631,6 +625,7 @@ class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO): class NIST_QC2(ZC706, _NIST_QC2_RTIO): def __init__(self, acpki, drtio100mhz): ZC706.__init__(self, acpki) + self.submodules += SMAClkinForward(self.platform) _NIST_QC2_RTIO.__init__(self) class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO): -- 2.44.1 From 9ac1338a323fcf4899e8a9e9601a24d140e09624 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 11 Jan 2023 15:12:15 +0800 Subject: [PATCH 05/30] test_dma: remove rtio cd --- src/gateware/test_dma.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gateware/test_dma.py b/src/gateware/test_dma.py index 0381664..c0786a3 100644 --- a/src/gateware/test_dma.py +++ b/src/gateware/test_dma.py @@ -229,7 +229,7 @@ class TestDMA(unittest.TestCase): do_dma(tb.dut, 0), monitor(), (None for _ in range(70)), tb.memory.ar(), tb.memory.r() - ]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8}) + ]}, {"sys": 8, "rsys": 8, "rio": 8, "rio_phy": 8}) correct_changes = [(timestamp + 11, channel) for channel, timestamp, _, _ in test_writes_full_stack] -- 2.44.1 From 4bf99bc63fc4e48678944792841e66040ac127be Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 12 Jan 2023 12:01:43 +0800 Subject: [PATCH 06/30] zc706: remove pll_reset --- src/gateware/zc706.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 10a2039..45dcbad 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -29,7 +29,6 @@ import drtio_aux_controller class SYSCRG(Module, AutoCSR): def __init__(self, platform): - self.pll_reset = CSRStorage(reset=1) self.pll_locked = CSRStatus() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -55,7 +54,7 @@ class SYSCRG(Module, AutoCSR): # VCO @ 1GHz when using 125MHz input p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, i_CLKFBIN=self.cd_sys.clk, - i_RST=self.pll_reset.storage, + i_RST=0, o_CLKFBOUT=sys_clk, -- 2.44.1 From 2cb4285a37d23a75180f33adfd50ab6ea31e595f Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 12 Jan 2023 12:43:05 +0800 Subject: [PATCH 07/30] remove removed rtioclockmultiplier --- src/gateware/kasli_soc.py | 1 - src/gateware/zc706.py | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index c7c9e1e..e774e63 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -15,7 +15,6 @@ from misoc.integration import cpu_interface from artiq.coredevice import jsondesc from artiq.gateware import rtio, eem_7series from artiq.gateware.rtio.phy import ttl_simple -from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier from artiq.gateware.drtio.transceiver import gtx_7series from artiq.gateware.drtio.siphaser import SiPhaser7Series from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 45dcbad..9556e27 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -15,7 +15,7 @@ from misoc.cores import gpio from artiq.gateware import rtio, nist_clock, nist_qc2 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2 -from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path +from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path from artiq.gateware.drtio.transceiver import gtx_7series from artiq.gateware.drtio.siphaser import SiPhaser7Series from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer -- 2.44.1 From c7e409520a465ffe8bc7e89034930eeecfa5defc Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 12 Jan 2023 16:39:22 +0800 Subject: [PATCH 08/30] extract main clock signal from SYSCRG --- src/gateware/kasli_soc.py | 24 ++++++++++++------------ src/gateware/zc706.py | 24 ++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 14 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index e774e63..c573274 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -26,20 +26,11 @@ import acpki import drtio_aux_controller class SYSCRG(Module, AutoCSR): - def __init__(self, platform): + def __init__(self, platform, main_clk): self.pll_locked = CSRStatus() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - clk_synth = platform.request("cdr_clk_clean_fabric") - clk_synth_se = Signal() - platform.add_period_constraint(clk_synth.p, 8.0) - self.specials += [ - Instance("IBUFGDS", - p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", - i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se), - ] - pll_locked = Signal() sys_clk = Signal() sys4x_clk = Signal() @@ -50,7 +41,7 @@ class SYSCRG(Module, AutoCSR): p_BANDWIDTH="HIGH", p_REF_JITTER1=0.001, p_CLKIN1_PERIOD=8.0, - i_CLKIN1=clk_synth_se, + i_CLKIN1=main_clk, i_CLKINSEL=1, # VCO @ 1.5GHz when using 125MHz input @@ -128,8 +119,17 @@ class GenericStandalone(SoCCore): self.rustc_cfg["has_si5324"] = None self.rustc_cfg["si5324_soft_reset"] = None + clk_synth = platform.request("cdr_clk_clean_fabric") + clk_synth_se = Signal() + platform.add_period_constraint(clk_synth.p, 8.0) + self.specials += [ + Instance("IBUFGDS", + p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", + i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se), + ] + self.crg = self.ps7 # HACK for eem_7series to find the clock - self.submodules.sys_crg = SYSCRG(self.platform) + self.submodules.sys_crg = SYSCRG(self.platform, clk_synth_se) self.csr_devices.append("sys_crg") # another hack since ps7 itself does not have cd_sys anymore self.crg.cd_sys = self.sys_crg.cd_sys diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 9556e27..251676b 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -28,7 +28,7 @@ import drtio_aux_controller class SYSCRG(Module, AutoCSR): - def __init__(self, platform): + def __init__(self, platform, main_clk): self.pll_locked = CSRStatus() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -148,7 +148,27 @@ class ZC706(SoCCore): ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) - self.submodules.sys_crg = SYSCRG(self.platform) + platform.add_extension(si5324_fmc33) + self.comb += platform.request("si5324_33").rst_n.eq(1) + + cdr_clk = Signal() + cdr_clk_buf = Signal() + si5324_out = platform.request("si5324_clkout") + platform.add_period_constraint(si5324_out.p, 8.0) + self.specials += [ + Instance("IBUFDS_GTE2", + i_I=si5324_out.p, i_IB=si5324_out.n, + o_O=cdr_clk, + p_CLKCM_CFG="0b1", + p_CLKRCV_TRST="0b1", + p_CLKSWING_CFG="0b11"), + Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf) + ] + self.rustc_cfg["has_si5324"] = None + self.rustc_cfg["si5324_as_synthesizer"] = None + self.rustc_cfg["si5324_soft_reset"] = None + + self.submodules.sys_crg = SYSCRG(self.platform, cdr_clk_buf) self.csr_devices.append("sys_crg") self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) -- 2.44.1 From 4aedc2fe61cc541c0811a4445b9783b1d50c00eb Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 12 Jan 2023 16:39:50 +0800 Subject: [PATCH 09/30] zc706: fix TSC, PLL parameters --- src/gateware/zc706.py | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 251676b..dacf33d 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -33,38 +33,35 @@ class SYSCRG(Module, AutoCSR): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - rtio_external_clk = Signal() - si5324_out = platform.request("si5324_clkout") - platform.add_period_constraint(si5324_out.p, 8.0) - self.specials += Instance("IBUFDS", - i_I=si5324_out.p, i_IB=si5324_out.n, - o_O=rtio_external_clk) - pll_locked = Signal() sys_clk = Signal() sys4x_clk = Signal() + fb_clk = Signal() self.specials += [ Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0, - i_CLKIN1=rtio_external_clk, + i_CLKIN1=main_clk, + i_CLKINSEL=1, # VCO @ 1GHz when using 125MHz input p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, - i_CLKFBIN=self.cd_sys.clk, + i_CLKFBIN=fb_clk, i_RST=0, - o_CLKFBOUT=sys_clk, + o_CLKFBOUT=fb_clk, - p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=sys4x_clk), + p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, + o_CLKOUT0=sys_clk, + p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, + o_CLKOUT1=sys4x_clk), Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked) ] - self.comb += self.pll_locked.status.eq(pll_locked) + self.comb += self.pll_locked.status.eq(pll_locked) class SMAClkinForward(Module): @@ -173,7 +170,7 @@ class ZC706(SoCCore): self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) def add_rtio(self, rtio_channels): - self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) self.csr_devices.append("rtio_core") @@ -240,7 +237,7 @@ class _MasterBase(SoCCore): rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") - self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) drtio_csr_group = [] drtioaux_csr_group = [] @@ -304,7 +301,7 @@ class _MasterBase(SoCCore): fix_serdes_timing_path(self.platform) def add_rtio(self, rtio_channels): - self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) self.csr_devices.append("rtio_core") @@ -365,7 +362,7 @@ class _SatelliteBase(SoCCore): platform.request("user_sma_mgt") ] - self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock self.submodules.drtio_transceiver = gtx_7series.GTX( -- 2.44.1 From 1aa6d0a16d6fce99c5f4df2f709a0d9154d20d9d Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 16 Jan 2023 18:13:55 +0800 Subject: [PATCH 10/30] test_dma: remove tsc mode --- src/gateware/test_dma.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gateware/test_dma.py b/src/gateware/test_dma.py index c0786a3..456205f 100644 --- a/src/gateware/test_dma.py +++ b/src/gateware/test_dma.py @@ -168,7 +168,7 @@ class FullStackTB(Module): bus = axi.Interface(ws*8) self.memory = AXIMemorySim(bus, sequence) self.submodules.dut = dma.DMA(bus) - self.submodules.tsc = rtio.TSC("async") + self.submodules.tsc = rtio.TSC() self.submodules.rtio = rtio.Core(self.tsc, rtio_channels) self.comb += self.dut.cri.connect(self.rtio.cri) -- 2.44.1 From b26731d83ce47f8619495fa18d10f72aeeb3e4e3 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 16 Jan 2023 18:14:14 +0800 Subject: [PATCH 11/30] flake: update dependencies --- flake.lock | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/flake.lock b/flake.lock index 0d55278..609f5ef 100644 --- a/flake.lock +++ b/flake.lock @@ -11,11 +11,11 @@ "src-pythonparser": "src-pythonparser" }, "locked": { - "lastModified": 1672816435, - "narHash": "sha256-cH2i+1eoJ+K9rAxctVjUR5oNWi54USjbtXPYj5a0j7A=", - "ref": "refs/heads/master", - "rev": "1be7e2a2e1d142802a52792865b19c8874fd0e9d", - "revCount": 8257, + "lastModified": 1673758995, + "narHash": "sha256-Nl00lPjySWyui12fGhU6/BiBZZVScI19ux3I+EGT4YM=", + "ref": "master", + "rev": "e9c65abebe8ce6912479b0a7334a813ae581458b", + "revCount": 8305, "type": "git", "url": "https://github.com/m-labs/artiq.git" }, @@ -68,11 +68,11 @@ "mozilla-overlay": { "flake": false, "locked": { - "lastModified": 1664789696, - "narHash": "sha256-UGWJHQShiwLCr4/DysMVFrYdYYHcOqAOVsWNUu+l6YU=", + "lastModified": 1672878308, + "narHash": "sha256-0+fl6PHokhtSV+w58z2QD2rTf8QhcOGsT9o4LwHHZHE=", "owner": "mozilla", "repo": "nixpkgs-mozilla", - "rev": "80627b282705101e7b38e19ca6e8df105031b072", + "rev": "d38863db88e100866b3e494a651ee4962b762fcc", "type": "github" }, "original": { @@ -115,11 +115,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1669735802, - "narHash": "sha256-qtG/o/i5ZWZLmXw108N2aPiVsxOcidpHJYNkT45ry9Q=", + "lastModified": 1673345971, + "narHash": "sha256-4DfFcKLRfVUTyuGrGNNmw37IeIZSoku9tgTVmu/iD98=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "731cc710aeebecbf45a258e977e8b68350549522", + "rev": "54644f409ab471e87014bb305eac8c50190bcf48", "type": "github" }, "original": { @@ -144,11 +144,11 @@ ] }, "locked": { - "lastModified": 1669369686, - "narHash": "sha256-YHez+S3PTUgtuliUNB5WM+RXcj8RKLbHVRvOgELSkwU=", + "lastModified": 1673433867, + "narHash": "sha256-a7Oq35YoDzPtISbqAsaT+2/v15HZ7G1q0ukXmKWdb7Q=", "owner": "m-labs", "repo": "sipyco", - "rev": "98db6eacb084c2c5280fb653bee3d313e3ca6df8", + "rev": "38f8f4185d7db6b68bd7f71546da9077b1e2561c", "type": "github" }, "original": { @@ -160,11 +160,11 @@ "src-migen": { "flake": false, "locked": { - "lastModified": 1662111470, - "narHash": "sha256-IPyhoFZLhY8d3jHB8jyvGdbey7V+X5eCzBZYSrJ18ec=", + "lastModified": 1673433200, + "narHash": "sha256-ribBG06gsucz5oBS+O6aL8s2oJjx+qfl+vXmspts8gg=", "owner": "m-labs", "repo": "migen", - "rev": "639e66f4f453438e83d86dc13491b9403bbd8ec6", + "rev": "f3e9145c9825514a1b4225378936569da4df8e12", "type": "github" }, "original": { @@ -176,11 +176,11 @@ "src-misoc": { "flake": false, "locked": { - "lastModified": 1669779825, - "narHash": "sha256-l3lyy6dmbivo9Tppb08KHSyU89ZZG1CCcSjPlNRD210=", - "ref": "master", - "rev": "2c255775f732a41ba1a512ab3d2547af4e25f674", - "revCount": 2435, + "lastModified": 1671158014, + "narHash": "sha256-50w0K2E2ympYrG1Tte/HVbsp4FS2U+yohqZByXTOo4I=", + "ref": "refs/heads/master", + "rev": "26f039f9f6931a20a04ccd0f0a5402f67f553916", + "revCount": 2436, "submodules": true, "type": "git", "url": "https://github.com/m-labs/misoc.git" @@ -218,7 +218,7 @@ "locked": { "lastModified": 1669819016, "narHash": "sha256-WvNMUekL4Elc55RdqX8XP43QPnBrK8Rbd0bsoI61E5U=", - "ref": "refs/heads/master", + "ref": "master", "rev": "67dbb5932fa8ff5f143983476f741f945871d286", "revCount": 624, "type": "git", -- 2.44.1 From 3194b772ae85623556d3c1d7cc9d5ad3ffbf513e Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 16 Jan 2023 18:14:56 +0800 Subject: [PATCH 12/30] move clocking to zynq_clocking add clock-switching FSM restore order --- src/gateware/kasli_soc.py | 58 ++++------------ src/gateware/zc706.py | 32 +++++---- src/gateware/zynq_clocking.py | 109 +++++++++++++++++++++++++++++++ src/runtime/src/rtio_clocking.rs | 13 ++-- 4 files changed, 146 insertions(+), 66 deletions(-) create mode 100644 src/gateware/zynq_clocking.py diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index c573274..2d533b7 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -24,46 +24,9 @@ import dma import analyzer import acpki import drtio_aux_controller +import zynq_clocking -class SYSCRG(Module, AutoCSR): - def __init__(self, platform, main_clk): - self.pll_locked = CSRStatus() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - pll_locked = Signal() - sys_clk = Signal() - sys4x_clk = Signal() - fb_clk = Signal() - self.specials += [ - Instance("PLLE2_ADV", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - p_BANDWIDTH="HIGH", - p_REF_JITTER1=0.001, - p_CLKIN1_PERIOD=8.0, - i_CLKIN1=main_clk, - i_CLKINSEL=1, - - # VCO @ 1.5GHz when using 125MHz input - p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, - i_CLKFBIN=fb_clk, - i_RST=0, - - o_CLKFBOUT=fb_clk, - - p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=sys4x_clk, - - p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=sys_clk), - Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), - - AsyncResetSynchronizer(self.cd_sys, ~pll_locked), - ] - self.comb += self.pll_locked.status.eq(pll_locked) - - eem_iostandard_dict = { 0: "LVDS_25", 1: "LVDS_25", @@ -129,7 +92,7 @@ class GenericStandalone(SoCCore): ] self.crg = self.ps7 # HACK for eem_7series to find the clock - self.submodules.sys_crg = SYSCRG(self.platform, clk_synth_se) + self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se) self.csr_devices.append("sys_crg") # another hack since ps7 itself does not have cd_sys anymore self.crg.cd_sys = self.sys_crg.cd_sys @@ -149,7 +112,7 @@ class GenericStandalone(SoCCore): self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) - self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels) self.csr_devices.append("rtio_core") @@ -219,8 +182,10 @@ class GenericMaster(SoCCore): self.csr_devices.append("drtio_transceiver") self.crg = self.ps7 # HACK for eem_7series to find the clock - self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq) - self.csr_devices.append("rtio_crg") + self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.drtio_transceiver.gtps[0].txoutclk) + self.csr_devices.append("sys_crg") + # another hack since ps7 itself does not have cd_sys anymore + self.crg.cd_sys = self.sys_crg.cd_sys self.rustc_cfg["has_si5324"] = None self.rustc_cfg["si5324_soft_reset"] = None @@ -239,7 +204,7 @@ class GenericMaster(SoCCore): self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) - self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) drtio_csr_group = [] drtioaux_csr_group = [] @@ -334,9 +299,8 @@ class GenericSatellite(SoCCore): platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") self.crg = self.ps7 # HACK for eem_7series to find the clock - self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq) - self.csr_devices.append("rtio_crg") - self.rustc_cfg["has_rtio_crg"] = None + self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.drtio_transceiver.gtps[0].txoutclk) + self.csr_devices.append("sys_crg") data_pads = [platform.request("sfp", i) for i in range(4)] @@ -360,7 +324,7 @@ class GenericSatellite(SoCCore): self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.rtio_channels.append(rtio.LogChannel()) - self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) drtioaux_csr_group = [] drtioaux_memory_group = [] diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index dacf33d..095e47c 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -25,11 +25,14 @@ import dma import analyzer import acpki import drtio_aux_controller +import zynq_clocking class SYSCRG(Module, AutoCSR): - def __init__(self, platform, main_clk): + def __init__(self, platform, ps7, main_clk): self.pll_locked = CSRStatus() + self.pll_clksel = CSRStorage() + self.pll_reset = CSRStorage() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -37,31 +40,35 @@ class SYSCRG(Module, AutoCSR): sys_clk = Signal() sys4x_clk = Signal() fb_clk = Signal() + fclk_buf = Signal() self.specials += [ + Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=fclk_buf), Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, + p_BANDWIDTH="HIGH", + p_REF_JITTER1=0.001, + p_CLKIN1_PERIOD=8.0, i_CLKIN1=main_clk, + p_CLKIN2_PERIOD=8.0, i_CLKIN2=fclk_buf, + i_CLKINSEL=self.pll_clksel.storage, - p_REF_JITTER1=0.01, - p_CLKIN1_PERIOD=8.0, - i_CLKIN1=main_clk, - i_CLKINSEL=1, - - # VCO @ 1GHz when using 125MHz input - p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, + # VCO @ 1.5GHz when using 125MHz input + p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, i_CLKFBIN=fb_clk, - i_RST=0, + i_RST=self.pll_reset.storage, o_CLKFBOUT=fb_clk, - p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, + p_CLKOUT0_DIVIDE=12, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=sys_clk, - p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, + p_CLKOUT1_DIVIDE=3, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=sys4x_clk), Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked) ] self.comb += self.pll_locked.status.eq(pll_locked) + platform.add_period_constraint(fclk_buf, 8.) + platform.add_false_path_constraints(self.cd_sys.clk, fclk_buf, main_clk) class SMAClkinForward(Module): @@ -154,6 +161,7 @@ class ZC706(SoCCore): platform.add_period_constraint(si5324_out.p, 8.0) self.specials += [ Instance("IBUFDS_GTE2", + i_CEB=0, i_I=si5324_out.p, i_IB=si5324_out.n, o_O=cdr_clk, p_CLKCM_CFG="0b1", @@ -165,7 +173,7 @@ class ZC706(SoCCore): self.rustc_cfg["si5324_as_synthesizer"] = None self.rustc_cfg["si5324_soft_reset"] = None - self.submodules.sys_crg = SYSCRG(self.platform, cdr_clk_buf) + self.submodules.sys_crg = SYSCRG(self.platform, self.ps7, cdr_clk_buf) self.csr_devices.append("sys_crg") self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py new file mode 100644 index 0000000..92b9c60 --- /dev/null +++ b/src/gateware/zynq_clocking.py @@ -0,0 +1,109 @@ +from migen import * +from migen.genlib.cdc import MultiReg +from migen.genlib.resetsync import AsyncResetSynchronizer +from misoc.interconnect.csr import * + + +class ClockSwitchFSM(Module): + def __init__(self): + self.i_clk_sw = Signal() + + self.o_clk_sw = Signal() + self.o_reset = Signal() + + ### + + i_switch = Signal() + o_switch = Signal() + reset = Signal() + + # at 125MHz bootstrap cd, will get around 0.5ms + delay_counter = Signal(16, reset=0xFFFF) + + # register to prevent glitches + self.sync.bootstrap += [ + self.o_clk_sw.eq(o_switch), + self.o_reset.eq(reset), + ] + + self.o_clk_sw.attr.add("no_retiming") + self.o_reset.attr.add("no_retiming") + self.i_clk_sw.attr.add("no_retiming") + i_switch.attr.add("no_retiming") + + self.specials += MultiReg(self.i_clk_sw, i_switch, "bootstrap") + + fsm = ClockDomainsRenamer("bootstrap")(FSM(reset_state="START")) + + self.submodules += fsm + + fsm.act("START", + If(i_switch & ~o_switch, + NextState("RESET_START")) + ) + + fsm.act("RESET_START", + reset.eq(1), + If(delay_counter == 0, + NextValue(delay_counter, 0xFFFF), + NextState("CLOCK_SWITCH") + ).Else( + NextValue(delay_counter, delay_counter-1), + ) + ) + + fsm.act("CLOCK_SWITCH", + reset.eq(1), + NextValue(o_switch, 1), + NextValue(delay_counter, delay_counter-1), + If(delay_counter == 0, + NextState("START")) + ) + + +class SYSCRG(Module, AutoCSR): + def __init__(self, platform, ps7, main_clk): + self.clock_switch = CSRStorage() + self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + + pll_locked = Signal() + sys_clk = Signal() + sys4x_clk = Signal() + fb_clk = Signal() + fclk_buf = Signal() + + self.submodules.clk_sw_fsm = ClockSwitchFSM() + + self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage) + + self.specials += [ + Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk), + Instance("PLLE2_ADV", + p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, + p_BANDWIDTH="HIGH", + p_REF_JITTER1=0.001, + p_CLKIN1_PERIOD=8.0, i_CLKIN1=main_clk, + p_CLKIN2_PERIOD=8.0, i_CLKIN2=self.cd_bootstrap.clk, + i_CLKINSEL=self.clk_sw_fsm.o_clk_sw, + + # VCO @ 1.5GHz when using 125MHz input + p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, + i_CLKFBIN=fb_clk, + i_RST=self.clk_sw_fsm.o_reset, + + o_CLKFBOUT=fb_clk, + + p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0, + o_CLKOUT0=sys4x_clk, + + p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0, + o_CLKOUT1=sys_clk), + Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), + + AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]), + ] + platform.add_period_constraint(self.cd_bootstrap.clk, 8.) + platform.add_false_path_constraints(self.cd_sys.clk, self.cd_bootstrap.clk, main_clk) diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 49a6c31..732ee32 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -68,17 +68,16 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) { - timer.delay_ms(1); - let locked = unsafe { pl::csr::sys_crg::pll_locked_read() != 0 }; - if locked { - info!("RTIO PLL locked"); - } else { - panic!("RTIO PLL failed to lock"); + info!("Switching SYS clocks..."); + unsafe { + pl::csr::sys_crg::clock_switch_write(1); } - + timer.delay_ms(2); unsafe { pl::csr::rtio_core::reset_phy_write(1); } + // if it's not locked, it will hang at the CSR. + info!("SYS PLL locked"); } #[cfg(has_drtio)] -- 2.44.1 From ac459617a6cb3c9f40aee0affd0770b5a8377b4d Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 17 Jan 2023 18:22:59 +0800 Subject: [PATCH 13/30] rename clk signals, add "keep" attrs --- src/gateware/zynq_clocking.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index 92b9c60..12d1c99 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -68,9 +68,12 @@ class SYSCRG(Module, AutoCSR): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.cd_sys.clk.attr.add("keep") + pll_locked = Signal() - sys_clk = Signal() - sys4x_clk = Signal() + pll_sys = Signal() + pll_sys.attr.add("keep") + pll_sys4x = Signal() fb_clk = Signal() fclk_buf = Signal() @@ -96,12 +99,12 @@ class SYSCRG(Module, AutoCSR): o_CLKFBOUT=fb_clk, p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=sys4x_clk, + o_CLKOUT0=pll_sys4x, p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=sys_clk), - Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), + o_CLKOUT1=pll_sys), + Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]), ] -- 2.44.1 From ca102d69c3805e0cc1d474b15eb1c861bcc2606e Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 17 Jan 2023 18:24:28 +0800 Subject: [PATCH 14/30] add fix_serdes_timing_path --- src/gateware/kasli_soc.py | 3 ++- src/gateware/zynq_clocking.py | 5 ++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 2d533b7..45c67e8 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -14,6 +14,7 @@ from misoc.integration import cpu_interface from artiq.coredevice import jsondesc from artiq.gateware import rtio, eem_7series +from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path from artiq.gateware.rtio.phy import ttl_simple from artiq.gateware.drtio.transceiver import gtx_7series from artiq.gateware.drtio.siphaser import SiPhaser7Series @@ -90,13 +91,13 @@ class GenericStandalone(SoCCore): p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se), ] + fix_serdes_timing_path(platform) self.crg = self.ps7 # HACK for eem_7series to find the clock self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se) self.csr_devices.append("sys_crg") # another hack since ps7 itself does not have cd_sys anymore self.crg.cd_sys = self.sys_crg.cd_sys - self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) self.rtio_channels = [] has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index 12d1c99..c7b93ca 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -69,10 +69,10 @@ class SYSCRG(Module, AutoCSR): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.cd_sys.clk.attr.add("keep") + self.cd_bootstrap.clk.attr.add("keep") pll_locked = Signal() pll_sys = Signal() - pll_sys.attr.add("keep") pll_sys4x = Signal() fb_clk = Signal() fclk_buf = Signal() @@ -108,5 +108,4 @@ class SYSCRG(Module, AutoCSR): AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]), ] - platform.add_period_constraint(self.cd_bootstrap.clk, 8.) - platform.add_false_path_constraints(self.cd_sys.clk, self.cd_bootstrap.clk, main_clk) + platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk) -- 2.44.1 From 831079f95fa54b88d1ea8d37bc6fc19cd62c3e26 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 19 Jan 2023 14:22:22 +0800 Subject: [PATCH 15/30] rtio_clocking: PLL requires a bit more time to lock --- src/runtime/src/main.rs | 4 ++-- src/runtime/src/rtio_clocking.rs | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index 956a81d..b83b2a4 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -111,6 +111,8 @@ pub fn main_core0() { ram::init_alloc_core0(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); + info!("gateware ident: {}", identifier_read(&mut [0; 64])); + i2c::init(); #[cfg(feature = "target_kasli_soc")] @@ -141,9 +143,7 @@ pub fn main_core0() { }; rtio_clocking::init(&mut timer, &cfg); - init_gateware(); - info!("gateware ident: {}", identifier_read(&mut [0; 64])); task::spawn(report_async_rtio_errors()); diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 732ee32..4e15347 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -72,12 +72,13 @@ fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) { unsafe { pl::csr::sys_crg::clock_switch_write(1); } - timer.delay_ms(2); + timer.delay_ms(10); + // if it's not locked, it will hang at the CSR. unsafe { pl::csr::rtio_core::reset_phy_write(1); } - // if it's not locked, it will hang at the CSR. info!("SYS PLL locked"); + } #[cfg(has_drtio)] -- 2.44.1 From 0e74afe64fd858ad8559d96cb104de31b7b385f1 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 20 Jan 2023 14:40:15 +0800 Subject: [PATCH 16/30] satman: switch clocks --- src/satman/src/main.rs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index 76a2f58..d8a42b6 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -477,6 +477,13 @@ pub extern fn main_core0() -> i32 { } timer.delay_us(1500); // wait for CPLL/QPLL lock + info!("Switching SYS clocks..."); + unsafe { + csr::sys_crg::clock_switch_write(1); + } + + timer.delay_us(10_000); // wait for SYS PLL lock + unsafe { csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); } -- 2.44.1 From dba8194f09b60cc3a958d497665d08c126a14c41 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 20 Jan 2023 14:40:50 +0800 Subject: [PATCH 17/30] zc706: cleanup, support for clock switch --- src/gateware/zc706.py | 119 ++++++++++++++---------------------------- 1 file changed, 38 insertions(+), 81 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 095e47c..8a808f2 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -28,49 +28,6 @@ import drtio_aux_controller import zynq_clocking -class SYSCRG(Module, AutoCSR): - def __init__(self, platform, ps7, main_clk): - self.pll_locked = CSRStatus() - self.pll_clksel = CSRStorage() - self.pll_reset = CSRStorage() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - - pll_locked = Signal() - sys_clk = Signal() - sys4x_clk = Signal() - fb_clk = Signal() - fclk_buf = Signal() - self.specials += [ - Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=fclk_buf), - Instance("PLLE2_ADV", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - p_BANDWIDTH="HIGH", - p_REF_JITTER1=0.001, - p_CLKIN1_PERIOD=8.0, i_CLKIN1=main_clk, - p_CLKIN2_PERIOD=8.0, i_CLKIN2=fclk_buf, - i_CLKINSEL=self.pll_clksel.storage, - - # VCO @ 1.5GHz when using 125MHz input - p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, - i_CLKFBIN=fb_clk, - i_RST=self.pll_reset.storage, - - o_CLKFBOUT=fb_clk, - - p_CLKOUT0_DIVIDE=12, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=sys_clk, - p_CLKOUT1_DIVIDE=3, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=sys4x_clk), - Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked) - ] - self.comb += self.pll_locked.status.eq(pll_locked) - platform.add_period_constraint(fclk_buf, 8.) - platform.add_false_path_constraints(self.cd_sys.clk, fclk_buf, main_clk) - - class SMAClkinForward(Module): def __init__(self, platform): sma_clkin = platform.request("user_sma_clock") @@ -173,9 +130,8 @@ class ZC706(SoCCore): self.rustc_cfg["si5324_as_synthesizer"] = None self.rustc_cfg["si5324_soft_reset"] = None - self.submodules.sys_crg = SYSCRG(self.platform, self.ps7, cdr_clk_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, cdr_clk_buf) self.csr_devices.append("sys_crg") - self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) def add_rtio(self, rtio_channels): self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) @@ -215,20 +171,17 @@ class _MasterBase(SoCCore): self.acpki = acpki self.rustc_cfg = dict() + clk_freq = 100e6 if drtio100mhz else 125e6 + platform = zc706.Platform() prepare_zc706_platform(platform) ident = self.__class__.__name__ if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) platform.add_extension(si5324_fmc33) - self.sys_clk_freq = 125e6 - rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq - - platform = self.platform - self.comb += platform.request("sfp_tx_disable_n").eq(1) data_pads = [ platform.request("sfp"), @@ -241,11 +194,20 @@ class _MasterBase(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, - sys_clk_freq=self.sys_clk_freq, - rtio_clk_freq=rtio_clk_freq) + clk_freq=clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) + txout_buf = Signal() + self.specials += Instance( + "BUFG", + i_I=self.drtio_transceiver.gtxs[0].txoutclk, + o_O=txout_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG( + self.platform, + self.ps7, + txout_buf) + self.csr_devices.append("sys_crg") drtio_csr_group = [] drtioaux_csr_group = [] @@ -288,25 +250,18 @@ class _MasterBase(SoCCore): self.rustc_cfg["has_si5324"] = None self.rustc_cfg["si5324_as_synthesizer"] = None - rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) gtx0 = self.drtio_transceiver.gtxs[0] - platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) - platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, gtx0.txoutclk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel # (Each channel performs single-lane phase alignment for RX) for gtx in self.drtio_transceiver.gtxs[1:]: - platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk) + gtx0.txoutclk, gtx.rxoutclk) - self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq) - self.csr_devices.append("rtio_crg") - fix_serdes_timing_path(self.platform) + fix_serdes_timing_path(platform) def add_rtio(self, rtio_channels): self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) @@ -331,7 +286,7 @@ class _MasterBase(SoCCore): self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri] + self.drtio_cri, - mode="sync", enable_routing=True) + enable_routing=True) self.csr_devices.append("cri_con") self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) @@ -350,19 +305,17 @@ class _SatelliteBase(SoCCore): self.acpki = acpki self.rustc_cfg = dict() + clk_freq = 100e6 if drtio100mhz else 125e6 + platform = zc706.Platform() prepare_zc706_platform(platform) ident = self.__class__.__name__ if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) platform.add_extension(si5324_fmc33) - self.sys_clk_freq = 125e6 - rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq - platform = self.platform - # SFP self.comb += platform.request("sfp_tx_disable_n").eq(0) data_pads = [ @@ -376,10 +329,21 @@ class _SatelliteBase(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, - sys_clk_freq=self.sys_clk_freq, - rtio_clk_freq=rtio_clk_freq) + clk_freq=clk_freq) self.csr_devices.append("drtio_transceiver") + txout_buf = Signal() + txout_buf.attr.add("keep") + self.specials += Instance( + "BUFG", + i_I=self.drtio_transceiver.gtxs[0].txoutclk, + o_O=txout_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG( + self.platform, + self.ps7, + txout_buf) + self.csr_devices.append("sys_crg") + drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] @@ -437,7 +401,7 @@ class _SatelliteBase(SoCCore): ultrascale=False, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) + self.sys_crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.csr_devices.append("si5324_rst_n") @@ -448,22 +412,15 @@ class _SatelliteBase(SoCCore): # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) gtx0 = self.drtio_transceiver.gtxs[0] - platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) - platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, gtx0.txoutclk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel # (Each channel performs single-lane phase alignment for RX) for gtx in self.drtio_transceiver.gtxs[1:]: - platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, gtx.rxoutclk) + self.sys_crg.cd_sys.clk, gtx.rxoutclk) - self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq) - self.csr_devices.append("rtio_crg") - self.rustc_cfg["has_rtio_crg"] = None - fix_serdes_timing_path(self.platform) + fix_serdes_timing_path(platform) def add_rtio(self, rtio_channels): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) @@ -485,7 +442,7 @@ class _SatelliteBase(SoCCore): self.submodules.cri_con = rtio.CRIInterconnectShared( [self.drtiosat.cri], [self.local_io.cri] + self.drtio_cri, - mode="sync", enable_routing=True) + enable_routing=True) self.csr_devices.append("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) -- 2.44.1 From aa0760e4abba2851925f380cd708113495810cba Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 20 Jan 2023 14:41:35 +0800 Subject: [PATCH 18/30] kasli_soc: support clock switch on drtio configs --- src/gateware/kasli_soc.py | 52 ++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 45c67e8..fe526be 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -154,8 +154,7 @@ class GenericStandalone(SoCCore): class GenericMaster(SoCCore): def __init__(self, description, acpki=False): - sys_clk_freq = 125e6 - rtio_clk_freq = description["rtio_frequency"] + clk_freq = description["rtio_frequency"] self.acpki = acpki self.rustc_cfg = dict() @@ -167,7 +166,7 @@ class GenericMaster(SoCCore): ident = description["variant"] if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") @@ -179,14 +178,20 @@ class GenericMaster(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("clk_gtp"), pads=data_pads, - sys_clk_freq=sys_clk_freq) + clk_freq=clk_freq) self.csr_devices.append("drtio_transceiver") - self.crg = self.ps7 # HACK for eem_7series to find the clock - self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.drtio_transceiver.gtps[0].txoutclk) + txout_buf = Signal() + txout_buf.attr.add("keep") + self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, + self.ps7, + txout_buf) self.csr_devices.append("sys_crg") + self.crg = self.ps7 # HACK for eem_7series to find the clock # another hack since ps7 itself does not have cd_sys anymore self.crg.cd_sys = self.sys_crg.cd_sys + fix_serdes_timing_path(platform) self.rustc_cfg["has_si5324"] = None self.rustc_cfg["si5324_soft_reset"] = None @@ -281,8 +286,7 @@ class GenericMaster(SoCCore): class GenericSatellite(SoCCore): def __init__(self, description, acpki=False): - sys_clk_freq = 125e6 - rtio_clk_freq = description["rtio_frequency"] + clk_freq = description["rtio_frequency"] self.acpki = acpki self.rustc_cfg = dict() @@ -294,23 +298,30 @@ class GenericSatellite(SoCCore): ident = description["variant"] if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") self.crg = self.ps7 # HACK for eem_7series to find the clock - self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.drtio_transceiver.gtps[0].txoutclk) - self.csr_devices.append("sys_crg") - + data_pads = [platform.request("sfp", i) for i in range(4)] self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("clk_gtp"), pads=data_pads, - sys_clk_freq=sys_clk_freq) + clk_freq=clk_freq) self.csr_devices.append("drtio_transceiver") + txout_buf = Signal() + txout_buf.attr.add("keep") + self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, + self.ps7, + txout_buf) + self.csr_devices.append("sys_crg") + self.crg.cd_sys = self.sys_crg.cd_sys + self.rtio_channels = [] has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) if has_grabber: @@ -396,7 +407,7 @@ class GenericSatellite(SoCCore): self.submodules.cri_con = rtio.CRIInterconnectShared( [self.drtiosat.cri], [self.local_io.cri] + self.drtio_cri, - mode="sync", enable_routing=True) + enable_routing=True) self.csr_devices.append("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) @@ -405,31 +416,22 @@ class GenericSatellite(SoCCore): self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels) self.csr_devices.append("rtio_moninj") - rtio_clk_period = 1e9/rtio_clk_freq - self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6) + rtio_clk_period = 1e9/clk_freq + self.rustc_cfg["rtio_frequency"] = str(clk_freq/1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("cdr_clk"), rx_synchronizer=self.rx_synchronizer, ultrascale=False, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) - platform.add_false_path_constraints( - self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.rustc_cfg["has_si5324"] = None self.rustc_cfg["has_siphaser"] = None self.rustc_cfg["si5324_soft_reset"] = None gtx0 = self.drtio_transceiver.gtxs[0] - platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) - platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.crg.cd_sys.clk, gtx0.txoutclk, gtx0.rxoutclk) - for gtx in self.drtio_transceiver.gtxs[1:]: - platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) - platform.add_false_path_constraints( - self.crg.cd_sys.clk, gtx.rxoutclk) if has_grabber: self.rustc_cfg["has_grabber"] = None -- 2.44.1 From 83d530d8acaedfb6b5459cff8587e06655daee1c Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 20 Jan 2023 17:02:11 +0800 Subject: [PATCH 19/30] rtio_clocking: init drtio first --- src/gateware/kasli_soc.py | 24 ++++++++++++++---------- src/gateware/zc706.py | 17 ++++++++--------- src/gateware/zynq_clocking.py | 17 ++++++++++++----- src/runtime/src/rtio_clocking.rs | 14 ++++++++------ src/satman/src/main.rs | 30 ++---------------------------- 5 files changed, 44 insertions(+), 58 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index fe526be..c4aeeab 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -182,11 +182,13 @@ class GenericMaster(SoCCore): self.csr_devices.append("drtio_transceiver") txout_buf = Signal() - txout_buf.attr.add("keep") - self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf) - self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, - self.ps7, - txout_buf) + gtx0 = self.drtio_transceiver.gtxs[0] + self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG( + self.platform, + self.ps7, + txout_buf, + clk_sw=gtx0.tx_init.done) self.csr_devices.append("sys_crg") self.crg = self.ps7 # HACK for eem_7series to find the clock # another hack since ps7 itself does not have cd_sys anymore @@ -314,11 +316,13 @@ class GenericSatellite(SoCCore): self.csr_devices.append("drtio_transceiver") txout_buf = Signal() - txout_buf.attr.add("keep") - self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf) - self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, - self.ps7, - txout_buf) + gtx0 = self.drtio_transceiver.gtxs[0] + self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG( + self.platform, + self.ps7, + txout_buf, + clk_sw=gtx0.tx_init.done) self.csr_devices.append("sys_crg") self.crg.cd_sys = self.sys_crg.cd_sys diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 8a808f2..6b2ebfe 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -199,14 +199,13 @@ class _MasterBase(SoCCore): self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) txout_buf = Signal() - self.specials += Instance( - "BUFG", - i_I=self.drtio_transceiver.gtxs[0].txoutclk, - o_O=txout_buf) + gtx0 = self.drtio_transceiver.gtxs[0] + self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, - txout_buf) + txout_buf, + clk_sw=gtx0.tx_init.done) self.csr_devices.append("sys_crg") drtio_csr_group = [] @@ -252,7 +251,6 @@ class _MasterBase(SoCCore): # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) - gtx0 = self.drtio_transceiver.gtxs[0] platform.add_false_path_constraints( gtx0.txoutclk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel @@ -334,14 +332,16 @@ class _SatelliteBase(SoCCore): txout_buf = Signal() txout_buf.attr.add("keep") + gtx0 = self.drtio_transceiver.gtxs[0] self.specials += Instance( "BUFG", - i_I=self.drtio_transceiver.gtxs[0].txoutclk, + i_I=gtx0.txoutclk, o_O=txout_buf) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, - txout_buf) + txout_buf, + clk_sw=gtx0.tx_init.done) self.csr_devices.append("sys_crg") drtioaux_csr_group = [] @@ -411,7 +411,6 @@ class _SatelliteBase(SoCCore): rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) - gtx0 = self.drtio_transceiver.gtxs[0] platform.add_false_path_constraints( gtx0.txoutclk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index c7b93ca..baed5e8 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -57,13 +57,15 @@ class ClockSwitchFSM(Module): NextValue(o_switch, 1), NextValue(delay_counter, delay_counter-1), If(delay_counter == 0, - NextState("START")) + NextState("END")) ) + fsm.act("END", + NextValue(o_switch, 1), + reset.eq(0)) class SYSCRG(Module, AutoCSR): - def __init__(self, platform, ps7, main_clk): - self.clock_switch = CSRStorage() + def __init__(self, platform, ps7, main_clk, clk_sw=None): self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -79,10 +81,15 @@ class SYSCRG(Module, AutoCSR): self.submodules.clk_sw_fsm = ClockSwitchFSM() - self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage) + if clk_sw is None: + self.clock_switch = CSRStorage() + self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage) + else: + self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw) self.specials += [ Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk), + # Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_sys.clk), Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_BANDWIDTH="HIGH", @@ -106,6 +113,6 @@ class SYSCRG(Module, AutoCSR): Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]), + AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0]), ] platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk) diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 4e15347..d9b37d3 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -66,13 +66,12 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { res } - -fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) { +#[cfg(not(has_drtio))] +fn init_rtio(timer: &mut GlobalTimer) { info!("Switching SYS clocks..."); unsafe { pl::csr::sys_crg::clock_switch_write(1); } - timer.delay_ms(10); // if it's not locked, it will hang at the CSR. unsafe { pl::csr::rtio_core::reset_phy_write(1); @@ -87,8 +86,10 @@ fn init_drtio(timer: &mut GlobalTimer) unsafe { pl::csr::drtio_transceiver::stable_clkin_write(1); } - timer.delay_ms(2); // wait for CPLL/QPLL lock + + timer.delay_ms(20); // wait for CPLL/QPLL/MMCM lock unsafe { + pl::csr::rtio_core::reset_phy_write(1); pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); } } @@ -228,8 +229,9 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) { } } - init_rtio(timer, clk); - #[cfg(has_drtio)] init_drtio(timer); + + #[cfg(not(has_drtio))] + init_rtio(timer); } \ No newline at end of file diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index d8a42b6..c1f70ef 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -390,25 +390,6 @@ fn drtiosat_process_errors() { } } - -#[cfg(has_rtio_crg)] -fn init_rtio_crg(timer: &mut GlobalTimer) { - unsafe { - csr::rtio_crg::pll_reset_write(0); - } - timer.delay_us(150); - let locked = unsafe { csr::rtio_crg::pll_locked_read() != 0 }; - if !locked { - error!("RTIO clock failed"); - } - else { - info!("RTIO PLL locked"); - } -} - -#[cfg(not(has_rtio_crg))] -fn init_rtio_crg(_timer: &mut GlobalTimer) { } - fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) { let now = timer.get_time(); let mut ts_ms = Milliseconds(*ts); @@ -472,22 +453,15 @@ pub extern fn main_core0() -> i32 { #[cfg(has_si5324)] si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324"); + info!("Switching SYS clocks..."); unsafe { csr::drtio_transceiver::stable_clkin_write(1); } - timer.delay_us(1500); // wait for CPLL/QPLL lock - - info!("Switching SYS clocks..."); - unsafe { - csr::sys_crg::clock_switch_write(1); - } - - timer.delay_us(10_000); // wait for SYS PLL lock + timer.delay_us(20_000); // wait for CPLL/QPLL/MMCM lock unsafe { csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); } - init_rtio_crg(&mut timer); #[cfg(has_drtio_routing)] let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()]; -- 2.44.1 From e6b9d5ebcb1a4567e4c635915dd7e1d9c55a87be Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 14 Feb 2023 11:13:51 +0800 Subject: [PATCH 20/30] set fclk before doing anything else --- src/runtime/src/main.rs | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index b83b2a4..d6c0fb1 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -22,6 +22,7 @@ use void::Void; use libconfig::Config; use libcortex_a9::l2c::enable_l2_cache; use libboard_artiq::{logger, identifier_read, init_gateware, pl}; +use embedded_hal::blocking::delay::DelayUs; const ASYNC_ERROR_COLLISION: u8 = 1 << 0; const ASYNC_ERROR_BUSY: u8 = 1 << 1; @@ -108,6 +109,9 @@ pub fn main_core0() { info!("NAR3/Zynq7000 starting..."); + init_gateware(); + timer.delay_us(500); // wait for FCLK to switch and MMCM to lock + ram::init_alloc_core0(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); @@ -141,9 +145,8 @@ pub fn main_core0() { Config::new_dummy() } }; - + rtio_clocking::init(&mut timer, &cfg); - init_gateware(); task::spawn(report_async_rtio_errors()); -- 2.44.1 From 062fa8e65d038b17a40f286ddd19366875df662d Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 14 Feb 2023 11:14:27 +0800 Subject: [PATCH 21/30] zynq_clocking: export clk switch status --- src/gateware/zynq_clocking.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index baed5e8..f596e04 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -70,6 +70,8 @@ class SYSCRG(Module, AutoCSR): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.current_clock = CSRStatus() + self.cd_sys.clk.attr.add("keep") self.cd_bootstrap.clk.attr.add("keep") @@ -86,10 +88,11 @@ class SYSCRG(Module, AutoCSR): self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage) else: self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw) + + platform.add_period_constraint(self.cd_bootstrap.clk, 8.0) self.specials += [ Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk), - # Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_sys.clk), Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_BANDWIDTH="HIGH", @@ -99,9 +102,11 @@ class SYSCRG(Module, AutoCSR): i_CLKINSEL=self.clk_sw_fsm.o_clk_sw, # VCO @ 1.5GHz when using 125MHz input + # FCLK on startup is ~42MHz, VCO below minimum + # do not use SYS before FCLK is configured from PS p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, i_CLKFBIN=fb_clk, - i_RST=self.clk_sw_fsm.o_reset, + i_RST=self.clk_sw_fsm.o_reset | ~ps7.fclk.reset_n[0], o_CLKFBOUT=fb_clk, @@ -113,6 +118,8 @@ class SYSCRG(Module, AutoCSR): Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0]), + AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0] | ~pll_locked) ] platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk) + + self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw) -- 2.44.1 From e86923b51d0bf895d1a33d7f89f7f4e3d60f66f0 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 14 Feb 2023 11:24:10 +0800 Subject: [PATCH 22/30] rtio_clocking: verify clock switch --- src/runtime/src/main.rs | 2 +- src/runtime/src/rtio_clocking.rs | 21 +++++++++++++++++++-- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index d6c0fb1..3421ee1 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -110,7 +110,7 @@ pub fn main_core0() { info!("NAR3/Zynq7000 starting..."); init_gateware(); - timer.delay_us(500); // wait for FCLK to switch and MMCM to lock + timer.delay_us(500); // wait for FCLK to switch and PLL to lock ram::init_alloc_core0(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index d9b37d3..00e51c9 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -1,4 +1,4 @@ -use log::{info, warn}; +use log::{info, warn, error}; use libboard_zynq::timer::GlobalTimer; use embedded_hal::blocking::delay::DelayMs; use libconfig::Config; @@ -73,6 +73,15 @@ fn init_rtio(timer: &mut GlobalTimer) { pl::csr::sys_crg::clock_switch_write(1); } // if it's not locked, it will hang at the CSR. + + timer.delay_ms(20); // wait for CPLL/QPLL/SYS PLL lock + let clk = unsafe { pl::csr::sys_crg::current_clock_read() }; + if clk == 1 { + info!("SYS CLK switched successfully"); + } + else { + error!("SYS CLK did not switch"); + } unsafe { pl::csr::rtio_core::reset_phy_write(1); } @@ -83,11 +92,19 @@ fn init_rtio(timer: &mut GlobalTimer) { #[cfg(has_drtio)] fn init_drtio(timer: &mut GlobalTimer) { + timer.delay_ms(1000); // wait for si output to really stabilize unsafe { pl::csr::drtio_transceiver::stable_clkin_write(1); } - timer.delay_ms(20); // wait for CPLL/QPLL/MMCM lock + timer.delay_ms(20); // wait for CPLL/QPLL/SYS PLL lock + let clk = unsafe { pl::csr::sys_crg::current_clock_read() }; + if clk == 1 { + info!("SYS CLK switched successfully"); + } + else { + error!("SYS CLK did not switch"); + } unsafe { pl::csr::rtio_core::reset_phy_write(1); pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); -- 2.44.1 From 39c9ef2940b60e599781d79027a895ae44842bf7 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 14 Feb 2023 11:54:47 +0800 Subject: [PATCH 23/30] satman: wait for FCLK, check clk switch --- src/satman/src/main.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index c1f70ef..15b2530 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -441,6 +441,7 @@ pub extern fn main_core0() -> i32 { log::set_max_level(log::LevelFilter::Info); init_gateware(); + timer.delay_us(500); // wait for FCLK to reset and PLL to lock info!("ARTIQ satellite manager starting..."); info!("gateware ident {}", identifier_read(&mut [0; 64])); @@ -458,6 +459,13 @@ pub extern fn main_core0() -> i32 { csr::drtio_transceiver::stable_clkin_write(1); } timer.delay_us(20_000); // wait for CPLL/QPLL/MMCM lock + let clk = unsafe { csr::sys_crg::current_clock_read() }; + if clk == 1 { + info!("SYS CLK switched successfully"); + } + else { + error!("SYS CLK did not switch"); + } unsafe { csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); -- 2.44.1 From ae0d7c807fcdca7cc4a592d002187366cd3e229b Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 16 Feb 2023 14:52:24 +0800 Subject: [PATCH 24/30] use external clock for bootstrap instead of fclk0 --- src/gateware/kasli_soc.py | 44 ++++++++++++++++++++++---------- src/gateware/zc706.py | 41 ++++++++++++++++++++++++++++- src/gateware/zynq_clocking.py | 21 ++++++++------- src/runtime/src/main.rs | 2 -- src/runtime/src/rtio_clocking.rs | 2 +- src/satman/src/main.rs | 1 + 6 files changed, 83 insertions(+), 28 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index c4aeeab..809818e 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -61,6 +61,23 @@ class SMAClkinForward(Module): ] +class GTP125BootstrapClock(Module): + def __init__(self, platform): + self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True) + self.cd_bootstrap.clk.attr.add("keep") + + bootstrap_125 = platform.request("clk125_gtp") + bootstrap_se = Signal() + platform.add_period_constraint(bootstrap_125.p, 8.0) + self.specials += [ + Instance("IBUFDS_GTE2", + p_CLKSWING_CFG="0b11", + i_CEB=0, + i_I=bootstrap_125.p, i_IB=bootstrap_125.n, o_O=bootstrap_se), + Instance("BUFG", i_I=bootstrap_se, o_O=self.cd_bootstrap.clk) + ] + + class GenericStandalone(SoCCore): def __init__(self, description, acpki=False): self.acpki = acpki @@ -75,9 +92,6 @@ class GenericStandalone(SoCCore): ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) - platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") - platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - self.submodules += SMAClkinForward(self.platform) self.rustc_cfg["has_si5324"] = None @@ -86,15 +100,17 @@ class GenericStandalone(SoCCore): clk_synth = platform.request("cdr_clk_clean_fabric") clk_synth_se = Signal() platform.add_period_constraint(clk_synth.p, 8.0) - self.specials += [ - Instance("IBUFGDS", + + self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", - i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se), - ] + i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se) fix_serdes_timing_path(platform) + self.submodules.bootstrap = GTP125BootstrapClock(self.platform) self.crg = self.ps7 # HACK for eem_7series to find the clock self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se) + platform.add_false_path_constraints( + self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") # another hack since ps7 itself does not have cd_sys anymore self.crg.cd_sys = self.sys_crg.cd_sys @@ -168,9 +184,6 @@ class GenericMaster(SoCCore): ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) - platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") - platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - self.submodules += SMAClkinForward(self.platform) data_pads = [platform.request("sfp", i) for i in range(4)] @@ -184,6 +197,8 @@ class GenericMaster(SoCCore): txout_buf = Signal() gtx0 = self.drtio_transceiver.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + + self.submodules.bootstrap = GTP125BootstrapClock(self.platform) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, @@ -193,6 +208,8 @@ class GenericMaster(SoCCore): self.crg = self.ps7 # HACK for eem_7series to find the clock # another hack since ps7 itself does not have cd_sys anymore self.crg.cd_sys = self.sys_crg.cd_sys + platform.add_false_path_constraints( + self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) fix_serdes_timing_path(platform) self.rustc_cfg["has_si5324"] = None @@ -302,9 +319,6 @@ class GenericSatellite(SoCCore): ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) - platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") - platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - self.crg = self.ps7 # HACK for eem_7series to find the clock data_pads = [platform.request("sfp", i) for i in range(4)] @@ -318,11 +332,15 @@ class GenericSatellite(SoCCore): txout_buf = Signal() gtx0 = self.drtio_transceiver.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + + self.submodules.bootstrap = GTP125BootstrapClock(self.platform) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, clk_sw=gtx0.tx_init.done) + platform.add_false_path_constraints( + self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") self.crg.cd_sys = self.sys_crg.cd_sys diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 6b2ebfe..732ba37 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -41,6 +41,36 @@ class SMAClkinForward(Module): ] +class CLK200BootstrapClock(Module): + def __init__(self, platform): + self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True) + self.cd_bootstrap.clk.attr.add("keep") + + + clk200 = platform.request("clk200") + clk200_se = Signal() + + pll_fb = Signal() + pll_clk125 = Signal() + self.specials += [ + Instance("IBUFDS", + i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se), + Instance("PLLE2_BASE", + p_CLKIN1_PERIOD=5.0, + i_CLKIN1=clk200_se, + i_CLKFBIN=pll_fb, + o_CLKFBOUT=pll_fb, + + # VCO @ 1GHz + p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, + + # 125MHz for bootstrap + p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clk125, + ), + Instance("BUFG", i_I=pll_clk125, o_O=self.cd_bootstrap.clk) + ] + + # The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply. # This also changes the I/O standard for some on-board LEDs. leds_fmc33 = [ @@ -129,8 +159,11 @@ class ZC706(SoCCore): self.rustc_cfg["has_si5324"] = None self.rustc_cfg["si5324_as_synthesizer"] = None self.rustc_cfg["si5324_soft_reset"] = None - + + self.submodules.bootstrap = CLK200BootstrapClock(platform) self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, cdr_clk_buf) + platform.add_false_path_constraints( + self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") def add_rtio(self, rtio_channels): @@ -201,11 +234,14 @@ class _MasterBase(SoCCore): txout_buf = Signal() gtx0 = self.drtio_transceiver.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + self.submodules.bootstrap = CLK200BootstrapClock(platform) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, clk_sw=gtx0.tx_init.done) + platform.add_false_path_constraints( + self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") drtio_csr_group = [] @@ -337,11 +373,14 @@ class _SatelliteBase(SoCCore): "BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + self.submodules.bootstrap = CLK200BootstrapClock(platform) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, clk_sw=gtx0.tx_init.done) + platform.add_false_path_constraints( + self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") drtioaux_csr_group = [] diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index f596e04..179c883 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -65,15 +65,18 @@ class ClockSwitchFSM(Module): class SYSCRG(Module, AutoCSR): - def __init__(self, platform, ps7, main_clk, clk_sw=None): - self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True) + def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6): + # assumes bootstrap clock is same freq as main and sys output self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.current_clock = CSRStatus() self.cd_sys.clk.attr.add("keep") - self.cd_bootstrap.clk.attr.add("keep") + + bootstrap_clk = ClockSignal("bootstrap") + + period = 1e9/freq pll_locked = Signal() pll_sys = Signal() @@ -88,17 +91,14 @@ class SYSCRG(Module, AutoCSR): self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage) else: self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw) - - platform.add_period_constraint(self.cd_bootstrap.clk, 8.0) self.specials += [ - Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk), Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_BANDWIDTH="HIGH", p_REF_JITTER1=0.001, - p_CLKIN1_PERIOD=8.0, i_CLKIN1=main_clk, - p_CLKIN2_PERIOD=8.0, i_CLKIN2=self.cd_bootstrap.clk, + p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk, + p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk, i_CLKINSEL=self.clk_sw_fsm.o_clk_sw, # VCO @ 1.5GHz when using 125MHz input @@ -106,7 +106,7 @@ class SYSCRG(Module, AutoCSR): # do not use SYS before FCLK is configured from PS p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, i_CLKFBIN=fb_clk, - i_RST=self.clk_sw_fsm.o_reset | ~ps7.fclk.reset_n[0], + i_RST=self.clk_sw_fsm.o_reset, o_CLKFBOUT=fb_clk, @@ -118,8 +118,7 @@ class SYSCRG(Module, AutoCSR): Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0] | ~pll_locked) + AsyncResetSynchronizer(self.cd_sys, ~pll_locked), ] - platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk) self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw) diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index 3421ee1..5e317a2 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -22,7 +22,6 @@ use void::Void; use libconfig::Config; use libcortex_a9::l2c::enable_l2_cache; use libboard_artiq::{logger, identifier_read, init_gateware, pl}; -use embedded_hal::blocking::delay::DelayUs; const ASYNC_ERROR_COLLISION: u8 = 1 << 0; const ASYNC_ERROR_BUSY: u8 = 1 << 1; @@ -110,7 +109,6 @@ pub fn main_core0() { info!("NAR3/Zynq7000 starting..."); init_gateware(); - timer.delay_us(500); // wait for FCLK to switch and PLL to lock ram::init_alloc_core0(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 00e51c9..1c39b66 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -92,7 +92,7 @@ fn init_rtio(timer: &mut GlobalTimer) { #[cfg(has_drtio)] fn init_drtio(timer: &mut GlobalTimer) { - timer.delay_ms(1000); // wait for si output to really stabilize + timer.delay_ms(100); // wait for si output to really stabilize unsafe { pl::csr::drtio_transceiver::stable_clkin_write(1); } diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index 15b2530..b1057ea 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -454,6 +454,7 @@ pub extern fn main_core0() -> i32 { #[cfg(has_si5324)] si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324"); + timer.delay_us(100_000); info!("Switching SYS clocks..."); unsafe { csr::drtio_transceiver::stable_clkin_write(1); -- 2.44.1 From cff2caa88f9687d0ac874746faac25294360021b Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 16 Feb 2023 15:09:16 +0800 Subject: [PATCH 25/30] zc706: support for 100mhz with new clocking system --- src/gateware/zc706.py | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 732ba37..0a174ae 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -42,16 +42,17 @@ class SMAClkinForward(Module): class CLK200BootstrapClock(Module): - def __init__(self, platform): + def __init__(self, platform, freq=125e6): self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True) self.cd_bootstrap.clk.attr.add("keep") - clk200 = platform.request("clk200") clk200_se = Signal() pll_fb = Signal() - pll_clk125 = Signal() + pll_clkout = Signal() + assert freq in [125e6, 100e6] + divide = int(1e9/freq) self.specials += [ Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se), @@ -64,10 +65,10 @@ class CLK200BootstrapClock(Module): # VCO @ 1GHz p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, - # 125MHz for bootstrap - p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clk125, + # 125MHz/100MHz for bootstrap + p_CLKOUT1_DIVIDE=divide, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clkout, ), - Instance("BUFG", i_I=pll_clk125, o_O=self.cd_bootstrap.clk) + Instance("BUFG", i_I=pll_clkout, o_O=self.cd_bootstrap.clk) ] @@ -234,12 +235,13 @@ class _MasterBase(SoCCore): txout_buf = Signal() gtx0 = self.drtio_transceiver.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) - self.submodules.bootstrap = CLK200BootstrapClock(platform) + self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done) + clk_sw=gtx0.tx_init.done, + freq=clk_freq) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") @@ -373,12 +375,13 @@ class _SatelliteBase(SoCCore): "BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) - self.submodules.bootstrap = CLK200BootstrapClock(platform) + self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done) + clk_sw=gtx0.tx_init.done, + freq=clk_freq) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") -- 2.44.1 From 5f10387684b5a270d15fea7720e0015759611600 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 17 Feb 2023 15:22:48 +0800 Subject: [PATCH 26/30] remove FCLK completely as it's not used --- src/gateware/zc706.py | 3 --- src/gateware/zynq_clocking.py | 4 +--- src/libboard_artiq/src/lib.rs | 23 ----------------------- src/runtime/src/main.rs | 4 +--- src/satman/src/main.rs | 5 +---- 5 files changed, 3 insertions(+), 36 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 0a174ae..13f7fee 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -123,9 +123,6 @@ def prepare_zc706_platform(platform): platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", ]) - platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") - platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - class ZC706(SoCCore): def __init__(self, acpki=False): diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index 179c883..72bb894 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -82,7 +82,6 @@ class SYSCRG(Module, AutoCSR): pll_sys = Signal() pll_sys4x = Signal() fb_clk = Signal() - fclk_buf = Signal() self.submodules.clk_sw_fsm = ClockSwitchFSM() @@ -102,8 +101,7 @@ class SYSCRG(Module, AutoCSR): i_CLKINSEL=self.clk_sw_fsm.o_clk_sw, # VCO @ 1.5GHz when using 125MHz input - # FCLK on startup is ~42MHz, VCO below minimum - # do not use SYS before FCLK is configured from PS + # 1.2GHz for 100MHz (zc706) p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, i_CLKFBIN=fb_clk, i_RST=self.clk_sw_fsm.o_reset, diff --git a/src/libboard_artiq/src/lib.rs b/src/libboard_artiq/src/lib.rs index b85481c..d330a7a 100644 --- a/src/libboard_artiq/src/lib.rs +++ b/src/libboard_artiq/src/lib.rs @@ -44,26 +44,3 @@ pub fn identifier_read(buf: &mut [u8]) -> &str { str::from_utf8_unchecked(&buf[..len as usize]) } } - -pub fn init_gateware() { - // Set up PS->PL clocks - slcr::RegisterBlock::unlocked(|slcr| { - // As we are touching the mux, the clock may glitch, so reset the PL. - slcr.fpga_rst_ctrl.write( - slcr::FpgaRstCtrl::zeroed() - .fpga0_out_rst(true) - .fpga1_out_rst(true) - .fpga2_out_rst(true) - .fpga3_out_rst(true) - ); - slcr.fpga0_clk_ctrl.write( - slcr::Fpga0ClkCtrl::zeroed() - .src_sel(slcr::PllSource::IoPll) - .divisor0(8) - .divisor1(1) - ); - slcr.fpga_rst_ctrl.write( - slcr::FpgaRstCtrl::zeroed() - ); - }); -} \ No newline at end of file diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index 5e317a2..fe47a04 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -21,7 +21,7 @@ use nb; use void::Void; use libconfig::Config; use libcortex_a9::l2c::enable_l2_cache; -use libboard_artiq::{logger, identifier_read, init_gateware, pl}; +use libboard_artiq::{logger, identifier_read, pl}; const ASYNC_ERROR_COLLISION: u8 = 1 << 0; const ASYNC_ERROR_BUSY: u8 = 1 << 1; @@ -108,8 +108,6 @@ pub fn main_core0() { info!("NAR3/Zynq7000 starting..."); - init_gateware(); - ram::init_alloc_core0(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index b1057ea..95350ff 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -22,7 +22,7 @@ use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, pri use libsupport_zynq::ram; #[cfg(has_si5324)] use libboard_artiq::si5324; -use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read, init_gateware}; +use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read}; use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache}; use libregister::{RegisterW, RegisterR}; @@ -439,9 +439,6 @@ pub extern fn main_core0() -> i32 { buffer_logger.set_uart_log_level(log::LevelFilter::Info); buffer_logger.register(); log::set_max_level(log::LevelFilter::Info); - - init_gateware(); - timer.delay_us(500); // wait for FCLK to reset and PLL to lock info!("ARTIQ satellite manager starting..."); info!("gateware ident {}", identifier_read(&mut [0; 64])); -- 2.44.1 From 02903503c63123b8caa3cbad10bf44c143864aa9 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 17 Feb 2023 15:33:52 +0800 Subject: [PATCH 27/30] libboard_artiq: fix warnings --- src/libboard_artiq/src/lib.rs | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/libboard_artiq/src/lib.rs b/src/libboard_artiq/src/lib.rs index d330a7a..454a819 100644 --- a/src/libboard_artiq/src/lib.rs +++ b/src/libboard_artiq/src/lib.rs @@ -29,8 +29,6 @@ pub mod drtioaux_async; pub mod mem; use core::{cmp, str}; -use libboard_zynq::slcr; -use libregister::RegisterW; pub fn identifier_read(buf: &mut [u8]) -> &str { unsafe { -- 2.44.1 From 65678fb4c2d2e5acdb2c9097825517f41885bf98 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 17 Feb 2023 15:34:01 +0800 Subject: [PATCH 28/30] kasli_soc: minor cleanup --- src/gateware/kasli_soc.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 809818e..d33e4e9 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -107,12 +107,12 @@ class GenericStandalone(SoCCore): fix_serdes_timing_path(platform) self.submodules.bootstrap = GTP125BootstrapClock(self.platform) - self.crg = self.ps7 # HACK for eem_7series to find the clock + self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") - # another hack since ps7 itself does not have cd_sys anymore + self.crg = self.ps7 # HACK for eem_7series to find the clock self.crg.cd_sys = self.sys_crg.cd_sys self.rtio_channels = [] @@ -206,7 +206,6 @@ class GenericMaster(SoCCore): clk_sw=gtx0.tx_init.done) self.csr_devices.append("sys_crg") self.crg = self.ps7 # HACK for eem_7series to find the clock - # another hack since ps7 itself does not have cd_sys anymore self.crg.cd_sys = self.sys_crg.cd_sys platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) @@ -319,8 +318,6 @@ class GenericSatellite(SoCCore): ident = "acpki_" + ident SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) - self.crg = self.ps7 # HACK for eem_7series to find the clock - data_pads = [platform.request("sfp", i) for i in range(4)] self.submodules.drtio_transceiver = gtx_7series.GTX( @@ -342,6 +339,7 @@ class GenericSatellite(SoCCore): platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") + self.crg = self.ps7 # HACK for eem_7series to find the clock self.crg.cd_sys = self.sys_crg.cd_sys self.rtio_channels = [] -- 2.44.1 From f7f956fc341b1ffb6ba948ad690d0807f921fa4f Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 17 Feb 2023 15:36:54 +0800 Subject: [PATCH 29/30] panic on sysclk not switched --- src/runtime/src/rtio_clocking.rs | 13 +++++-------- src/satman/src/main.rs | 12 +++++++++--- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 1c39b66..5340e6d 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -1,4 +1,4 @@ -use log::{info, warn, error}; +use log::{info, warn}; use libboard_zynq::timer::GlobalTimer; use embedded_hal::blocking::delay::DelayMs; use libconfig::Config; @@ -78,9 +78,8 @@ fn init_rtio(timer: &mut GlobalTimer) { let clk = unsafe { pl::csr::sys_crg::current_clock_read() }; if clk == 1 { info!("SYS CLK switched successfully"); - } - else { - error!("SYS CLK did not switch"); + } else { + panic!("SYS CLK did not switch"); } unsafe { pl::csr::rtio_core::reset_phy_write(1); @@ -92,7 +91,6 @@ fn init_rtio(timer: &mut GlobalTimer) { #[cfg(has_drtio)] fn init_drtio(timer: &mut GlobalTimer) { - timer.delay_ms(100); // wait for si output to really stabilize unsafe { pl::csr::drtio_transceiver::stable_clkin_write(1); } @@ -101,9 +99,8 @@ fn init_drtio(timer: &mut GlobalTimer) let clk = unsafe { pl::csr::sys_crg::current_clock_read() }; if clk == 1 { info!("SYS CLK switched successfully"); - } - else { - error!("SYS CLK did not switch"); + } else { + panic!("SYS CLK did not switch"); } unsafe { pl::csr::rtio_core::reset_phy_write(1); diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index 95350ff..ae79d83 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -25,6 +25,8 @@ use libboard_artiq::si5324; use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read}; use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache}; use libregister::{RegisterW, RegisterR}; +#[cfg(feature = "target_kasli_soc")] +use libboard_zynq::error_led::ErrorLED; use embedded_hal::blocking::delay::DelayUs; use core::sync::atomic::{AtomicBool, Ordering}; @@ -460,9 +462,8 @@ pub extern fn main_core0() -> i32 { let clk = unsafe { csr::sys_crg::current_clock_read() }; if clk == 1 { info!("SYS CLK switched successfully"); - } - else { - error!("SYS CLK did not switch"); + } else { + panic!("SYS CLK did not switch"); } unsafe { @@ -601,6 +602,11 @@ pub extern fn exception(_vect: u32, _regs: *const u32, pc: u32, ea: u32) { #[panic_handler] pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! { let id = MPIDR.read().cpu_id() as usize; + #[cfg(feature = "target_kasli_soc")] + { + let mut err_led = ErrorLED::error_led(); + err_led.toggle(true); + } print!("Core {} ", id); unsafe { if PANICKED[id] { -- 2.44.1 From f3ae8660d0b983c5cdcdb29b47ac576f9156f8c5 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 17 Feb 2023 15:51:38 +0800 Subject: [PATCH 30/30] remove out-of-scope error LED support for satellite --- src/satman/src/main.rs | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index ae79d83..de66c1a 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -25,8 +25,6 @@ use libboard_artiq::si5324; use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read}; use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache}; use libregister::{RegisterW, RegisterR}; -#[cfg(feature = "target_kasli_soc")] -use libboard_zynq::error_led::ErrorLED; use embedded_hal::blocking::delay::DelayUs; use core::sync::atomic::{AtomicBool, Ordering}; @@ -602,11 +600,6 @@ pub extern fn exception(_vect: u32, _regs: *const u32, pc: u32, ea: u32) { #[panic_handler] pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! { let id = MPIDR.read().cpu_id() as usize; - #[cfg(feature = "target_kasli_soc")] - { - let mut err_led = ErrorLED::error_led(); - err_led.toggle(true); - } print!("Core {} ", id); unsafe { if PANICKED[id] { -- 2.44.1