M-Labs/artiq-zynq
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RTIO/SYS Clock merge #212

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sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
Conversation 5 Commits 30 Files Changed 9 +9 -6
1 changed files with 9 additions and 6 deletions
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15
src/gateware/zynq_clocking.py
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@ -68,9 +68,12 @@ class SYSCRG(Module, AutoCSR):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.cd_sys.clk.attr.add("keep")
pll_locked = Signal() pll_locked = Signal()
sys_clk = Signal() pll_sys = Signal()
sys4x_clk = Signal() pll_sys.attr.add("keep")
pll_sys4x = Signal()
fb_clk = Signal() fb_clk = Signal()
fclk_buf = Signal() fclk_buf = Signal()
@ -96,12 +99,12 @@ class SYSCRG(Module, AutoCSR):
o_CLKFBOUT=fb_clk, o_CLKFBOUT=fb_clk,
p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0, p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=sys4x_clk, o_CLKOUT0=pll_sys4x,
p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0, p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=sys_clk), o_CLKOUT1=pll_sys),
Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]),
] ]