M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

RTIO/SYS Clock merge #212

Merged
sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
Conversation 5 Commits 30 Files Changed 9 +3 -5
1 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit 65678fb4c2 - Show all commits

8
src/gateware/kasli_soc.py
View File

@ -107,12 +107,12 @@ class GenericStandalone(SoCCore):
fix_serdes_timing_path(platform) fix_serdes_timing_path(platform)
self.submodules.bootstrap = GTP125BootstrapClock(self.platform) self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
self.crg = self.ps7 # HACK for eem_7series to find the clock
self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se) self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
self.csr_devices.append("sys_crg") self.csr_devices.append("sys_crg")
# another hack since ps7 itself does not have cd_sys anymore self.crg = self.ps7 # HACK for eem_7series to find the clock
self.crg.cd_sys = self.sys_crg.cd_sys self.crg.cd_sys = self.sys_crg.cd_sys
self.rtio_channels = [] self.rtio_channels = []
@ -206,7 +206,6 @@ class GenericMaster(SoCCore):
clk_sw=gtx0.tx_init.done) clk_sw=gtx0.tx_init.done)
self.csr_devices.append("sys_crg") self.csr_devices.append("sys_crg")
self.crg = self.ps7 # HACK for eem_7series to find the clock self.crg = self.ps7 # HACK for eem_7series to find the clock
# another hack since ps7 itself does not have cd_sys anymore
self.crg.cd_sys = self.sys_crg.cd_sys self.crg.cd_sys = self.sys_crg.cd_sys
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
@ -319,8 +318,6 @@ class GenericSatellite(SoCCore):
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
self.crg = self.ps7 # HACK for eem_7series to find the clock
data_pads = [platform.request("sfp", i) for i in range(4)] data_pads = [platform.request("sfp", i) for i in range(4)]
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
@ -342,6 +339,7 @@ class GenericSatellite(SoCCore):
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
self.csr_devices.append("sys_crg") self.csr_devices.append("sys_crg")
self.crg = self.ps7 # HACK for eem_7series to find the clock
self.crg.cd_sys = self.sys_crg.cd_sys self.crg.cd_sys = self.sys_crg.cd_sys
self.rtio_channels = [] self.rtio_channels = []