M-Labs/artiq-zynq
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RTIO/SYS Clock merge #212

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sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
Conversation 5 Commits 30 Files Changed 9 +1 -2
1 changed files with 1 additions and 2 deletions
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src/gateware/zc706.py
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@ -29,7 +29,6 @@ import drtio_aux_controller
class SYSCRG(Module, AutoCSR): class SYSCRG(Module, AutoCSR):
def __init__(self, platform): def __init__(self, platform):
self.pll_reset = CSRStorage(reset=1)
self.pll_locked = CSRStatus() self.pll_locked = CSRStatus()
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
@ -55,7 +54,7 @@ class SYSCRG(Module, AutoCSR):
# VCO @ 1GHz when using 125MHz input # VCO @ 1GHz when using 125MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=self.cd_sys.clk, i_CLKFBIN=self.cd_sys.clk,
i_RST=self.pll_reset.storage, i_RST=0,
o_CLKFBOUT=sys_clk, o_CLKFBOUT=sys_clk,