RTIO/SYS Clock merge #212
@ -33,38 +33,35 @@ class SYSCRG(Module, AutoCSR):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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rtio_external_clk = Signal()
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si5324_out = platform.request("si5324_clkout")
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platform.add_period_constraint(si5324_out.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=si5324_out.p, i_IB=si5324_out.n,
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o_O=rtio_external_clk)
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pll_locked = Signal()
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sys_clk = Signal()
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sys4x_clk = Signal()
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fb_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0,
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i_CLKIN1=rtio_external_clk,
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i_CLKIN1=main_clk,
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i_CLKINSEL=1,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_sys.clk,
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i_CLKFBIN=fb_clk,
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i_RST=0,
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o_CLKFBOUT=sys_clk,
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o_CLKFBOUT=fb_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=sys4x_clk),
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=sys_clk,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=sys4x_clk),
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Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked)
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]
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self.comb += self.pll_locked.status.eq(pll_locked)
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self.comb += self.pll_locked.status.eq(pll_locked)
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class SMAClkinForward(Module):
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@ -173,7 +170,7 @@ class ZC706(SoCCore):
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self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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@ -240,7 +237,7 @@ class _MasterBase(SoCCore):
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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@ -304,7 +301,7 @@ class _MasterBase(SoCCore):
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fix_serdes_timing_path(self.platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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@ -365,7 +362,7 @@ class _SatelliteBase(SoCCore):
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platform.request("user_sma_mgt")
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]
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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