M-Labs/artiq-zynq
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RTIO/SYS Clock merge #212

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sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
Conversation 5 Commits 30 Files Changed 9 +8
1 changed files with 8 additions and 0 deletions
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Showing only changes of commit 39c9ef2940 - Show all commits

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src/satman/src/main.rs
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@ -441,6 +441,7 @@ pub extern fn main_core0() -> i32 {
log::set_max_level(log::LevelFilter::Info);
init_gateware();
timer.delay_us(500); // wait for FCLK to reset and PLL to lock
info!("ARTIQ satellite manager starting...");
info!("gateware ident {}", identifier_read(&mut [0; 64]));
@ -458,6 +459,13 @@ pub extern fn main_core0() -> i32 {
csr::drtio_transceiver::stable_clkin_write(1);
}
timer.delay_us(20_000); // wait for CPLL/QPLL/MMCM lock
let clk = unsafe { csr::sys_crg::current_clock_read() };
if clk == 1 {
info!("SYS CLK switched successfully");
}
else {
error!("SYS CLK did not switch");
}
unsafe {
csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);