M-Labs/artiq-zynq
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RTIO/SYS Clock merge #212

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sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
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src/satman/src/main.rs
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@ -477,6 +477,13 @@ pub extern fn main_core0() -> i32 {
} }
timer.delay_us(1500); // wait for CPLL/QPLL lock timer.delay_us(1500); // wait for CPLL/QPLL lock
info!("Switching SYS clocks...");
unsafe {
csr::sys_crg::clock_switch_write(1);
}
timer.delay_us(10_000); // wait for SYS PLL lock
unsafe { unsafe {
csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
} }