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Support for DRTIO 100MHz #155

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sb10q merged 5 commits from mwojcik/artiq-zynq:drtio_100mhz into master 2021-12-03 17:19:42 +08:00
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mwojcik commented 2021-12-03 12:21:29 +08:00
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This works in tandem with ARTIQ PR for that - mainline needs to be merged first, due to siphaser assert.

This adds support for 100MHz DRTIO clock for zc706 and kasli-soc. PLL and VCO parameters have been checked against the datasheet. 100MHz is actually the lowest we can go with DRTIO clock because of minimum VCO frequency on Zynq (800MHz is the minimum, and that's the exact value here for siphaser).

For kasli-soc "rtio_frequency" key in JSON is used, for zc706 - additional variants have been created, since it's built with nix-build rather than calling a python module (otherwise I would use a command line option). Maybe there's a better solution for that?

This has been tested between KC705 and ZC706 over SMA, with both devices as master and satellite.

This works in tandem with ARTIQ PR for that - mainline needs to be merged first, due to siphaser assert. This adds support for 100MHz DRTIO clock for zc706 and kasli-soc. PLL and VCO parameters have been checked against the datasheet. 100MHz is actually the lowest we can go with DRTIO clock because of minimum VCO frequency on Zynq (800MHz is the minimum, and that's the exact value here for siphaser). For kasli-soc "rtio_frequency" key in JSON is used, for zc706 - additional variants have been created, since it's built with nix-build rather than calling a python module (otherwise I would use a command line option). Maybe there's a better solution for that? This has been tested between KC705 and ZC706 over SMA, with both devices as master and satellite.
mwojcik added 5 commits 2021-12-03 12:21:30 +08:00 
* si5324 settings for sat
* rtio_clocking: additional default 100mhz option
sb10q merged commit 31fb2b388a into master 2021-12-03 17:19:42 +08:00
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Reference: M-Labs/artiq-zynq#155
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