add switch for drtio 100mhz clock

src/gateware/zc706.py

@@ -127,7 +127,7 @@ def prepare_zc706_platform(platform):
 
 
 class ZC706(SoCCore):
-    def __init__(self, acpki=False):
+    def __init__(self, acpki=False, _drtio100mhz=False):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
@@ -181,7 +181,7 @@ class ZC706(SoCCore):
 
 
 class _MasterBase(SoCCore):
-    def __init__(self, acpki=False):
+    def __init__(self, acpki=False, drtio100mhz=False):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
@@ -195,6 +195,7 @@ class _MasterBase(SoCCore):
         platform.add_extension(si5324_fmc33)
 
         self.sys_clk_freq = 125e6
+        rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
 
         platform = self.platform
 
@@ -208,7 +209,8 @@ class _MasterBase(SoCCore):
         self.submodules.drtio_transceiver = gtx_7series.GTX(
             clock_pads=platform.request("si5324_clkout"),
             pads=data_pads,
-            sys_clk_freq=self.sys_clk_freq)
+            sys_clk_freq=self.sys_clk_freq,
+            rtio_clk_freq=rtio_clk_freq)
         self.csr_devices.append("drtio_transceiver")
 
         self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
@@ -313,7 +315,7 @@ class _MasterBase(SoCCore):
 
 
 class _SatelliteBase(SoCCore):
-    def __init__(self, acpki=False):
+    def __init__(self, acpki=False, drtio100mhz=False):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
@@ -327,6 +329,7 @@ class _SatelliteBase(SoCCore):
         platform.add_extension(si5324_fmc33)
 
         self.sys_clk_freq = 125e6
+        rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
         platform = self.platform
 
         # SFP
@@ -342,7 +345,8 @@ class _SatelliteBase(SoCCore):
         self.submodules.drtio_transceiver = gtx_7series.GTX(
             clock_pads=platform.request("si5324_clkout"),
             pads=data_pads,
-            sys_clk_freq=self.sys_clk_freq)
+            sys_clk_freq=self.sys_clk_freq,
+            rtio_clk_freq=rtio_clk_freq)
         self.csr_devices.append("drtio_transceiver")
 
         drtioaux_csr_group = []
@@ -399,7 +403,7 @@ class _SatelliteBase(SoCCore):
         self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("si5324_clkin"),
             rx_synchronizer=self.rx_synchronizer,
-            ultrascale=False,
+            ultrascale=True,
             rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
         platform.add_false_path_constraints(
             self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)
@@ -595,34 +599,33 @@ class _NIST_QC2_RTIO:
 
 
 class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki):
-        ZC706.__init__(self, acpki)
+    def __init__(self, acpki, drtio100mhz):
+        ZC706.__init__(self, acpki, drtio100mhz)
         _NIST_CLOCK_RTIO.__init__(self)
 
 class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki):
-        _MasterBase.__init__(self, acpki)
-
+    def __init__(self, acpki, drtio100mhz):
+        _MasterBase.__init__(self, acpki, drtio100mhz)
         _NIST_CLOCK_RTIO.__init__(self)
 
 class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki):
-        _SatelliteBase.__init__(self, acpki)
+    def __init__(self, acpki, drtio100mhz):
+        _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_CLOCK_RTIO.__init__(self)
 
 class NIST_QC2(ZC706, _NIST_QC2_RTIO):
-    def __init__(self, acpki):
-        ZC706.__init__(self, acpki)
+    def __init__(self, acpki, drtio100mhz):
+        ZC706.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
 class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
-    def __init__(self, acpki):
-        _MasterBase.__init__(self, acpki)
+    def __init__(self, acpki, drtio100mhz):
+        _MasterBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
 class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
-    def __init__(self, acpki):
-        _SatelliteBase.__init__(self, acpki)
+    def __init__(self, acpki, drtio100mhz):
+        _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
 
@@ -661,6 +664,8 @@ def main():
         help="build Rust compiler configuration into the specified file")
     parser.add_argument("-g", default=None,
         help="build gateware into the specified directory")
+    parser.add_argument("--drtio100mhz", action="store_true", default=False,
+        help="DRTIO variants only: use 100MHz DRTIO clock")
     parser.add_argument("-V", "--variant", default="nist_clock",
                         help="variant: "
                              "[acpki_]nist_clock/nist_qc2[_master/_satellite] "
@@ -676,7 +681,7 @@ def main():
     except KeyError:
         raise SystemExit("Invalid variant (-V/--variant)")
 
-    soc = cls(acpki=acpki)
+    soc = cls(acpki=acpki, drtio100mhz=args.drtio100mhz)
     soc.finalize()
 
     if args.r is not None: