Clean up warning take 2

Clean up comments and warning
Set fclk0 for ebaz4205
2024-11-01 17:28:53 -07:00 · 2024-11-01 17:26:46 -07:00 · 2024-11-01 17:22:05 -07:00
36 changed files with 354 additions and 1995 deletions
--- a/README.md
+++ b/README.md
@ -4,92 +4,60 @@ ARTIQ on Zynq
 How to use
 ----------
-1. [Install ARTIQ](https://m-labs.hk/artiq/manual/installing.html). Get the corresponding version to the ``artiq-zynq`` version you are targeting.
+1. Install the ARTIQ version that corresponds to the artiq-zynq version you are targeting.
-2. To obtain firmware binaries, use AFWS or build your own; see [the ARTIQ manual](https://m-labs.hk/artiq/manual/building_developing.html) for detailed instructions or skip to "Development" below. ZC706 variants only can also be downloaded from latest successful build on [Hydra](https://nixbld.m-labs.hk/).
+2. To obtain firmware binaries, select the latest successful build on [Hydra](https://nixbld.m-labs.hk/) for the targeted artiq-zynq version, or use AFWS. If using Hydra, search for the job named ``<board>-<variant>-sd`` (for example: ``zc706-nist_clock-sd`` or ``zc706-nist_qc2-sd``).
-3. Place ``boot.bin`` file at the root ``/`` of a FAT-formatted SD card.
+3. Place the ``boot.bin`` file, obtained from Hydra's "binary distribution" download link or from AFWS, at the root of a FAT-formatted SD card.
-4. Optionally, create a ``config.txt`` configuration file containing ``key=value`` pairs on each line and place it at the root of the SD card. See below for valid keys. The ``ip``, ``ip6`` and ``mac`` keys can be used to set networking information. If these keys are not found, the firmware will use default values which may or may not be compatible with your network.
+4. Optionally, create a ``config.txt`` configuration file at the root of the SD card containing ``key=value`` pairs on each line. Use the ``ip``, ``ip6`` and ``mac`` keys to respectively set the IPv4, IPv6 and MAC address of the board. Configuring an IPv6 address is entirely optional. If these keys are not found, the firmware will use default values that may or may not be compatible with your network.
-5. Insert the SD card into the board and set the board to boot from the SD card. For ZC706, this is achieved by placing the large DIP switch SW11 into the 00110 position. On Kasli-SoC, place the BOOT MODE switches to SD.
+5. Insert the SD card into the board and set up the board to boot from the SD card. For the ZC706, this is achieved by placing the large DIP switch SW11 in the 00110 position.
-6. Power up the board. After successful boot the firmware should respond to ping at its IP addresses. Boot output can be observed from UART at 115200bps 8-N-1.
+6. Power up the board. After the firmware starts successfully, it should respond to ping at its IP addresses, and boot messages can be observed from its UART at 115200bps.
-7. Create and use an ARTIQ device database as usual.
+7. Create and use an ARTIQ device database as usual, but set ``"target": "cortexa9"`` in the arguments of the core device.
 Configuration
 -------------
-Configuring the device is done using the ``config.txt`` text file at the root of the SD card plus optionally a ``config`` folder. When searching for a configuration key, the firmware first looks for a file named ``/config/[key].bin`` and, if it exists, returns the contents of that file. If not, it looks into ``/config.txt``, which should contain a list of ``key=value`` pairs, one per line. ``config.txt`` should be used for most keys but the ``config`` folder allows for setting configuration values which consist of binary data, such as the startup kernel.
+Configuring the device is done using the ``config.txt`` text file at the root of the SD card, plus the contents of the ``config`` folder. When searching for a configuration key, the firmware first looks for a file named ``/config/[key].bin`` and, if it exists, returns the contents of that file. If not, it looks into ``/config.txt``, which contains a list of ``key=value`` pairs, one per line. The ``config`` folder allows configuration values that consist in binary data, such as the startup kernel.
-The following configuration keys are available among others:
+The following configuration keys are available:
 - ``mac``: Ethernet MAC address.
 - ``ip``: IPv4 address.
 - ``ip6``: IPv6 address.
- ``idle_kernel``: idle kernel in ELF format (as produced by ``artiq_compile``).
+- ``startup``: startup kernel in ELF format (as produced by ``artiq_compile``).
 - ``startup_kernel``: startup kernel in ELF format (as produced by ``artiq_compile``).
 - ``rtio_clock``: source of RTIO clock; valid values are ``ext0_bypass`` and ``int_125``.
 - ``boot``: SD card "boot.bin" file, for replacing the boot firmware/gateware. Write only.
-See [ARTIQ manual](https://m-labs.hk/artiq/manual-beta/core_device.html#configuration-storage) for full list. Configurations can be read/written/removed with ``artiq_coremgmt``. Config erase is not implemented, as it isn't particularly useful.
+Configurations can be read/written/removed via ``artiq_coremgmt``. Config erase is
-
+not implemented as it seems not very useful.
 For convenience, the ``boot`` key can be used with ``artiq_coremgmt`` and a ``boot.bin`` file to replace firmware/gateware in a running system. This key is read-only. When loading ``boot.bin`` onto the SD card directly, place it at the root and not in the ``config`` folder.
 Development instructions
 ------------------------
-ARTIQ on Zynq is packaged using [Nix](https://nixos.org) Flakes. Install Nix 2.8+ and enable flakes by adding ``experimental-features = nix-command flakes`` to ``nix.conf`` (e.g. ``~/.config/nix/nix.conf``).
+ARTIQ on Zynq is packaged using the [Nix](https://nixos.org) Flakes system. Install Nix 2.8+ and enable flakes by adding ``experimental-features = nix-command flakes`` to ``nix.conf`` (e.g. ``~/.config/nix/nix.conf``).
-**Pure build with Nix:**
+Pure build with Nix and execution on a remote JTAG server:
 ```shell
-nix build .#zc706-nist_clock-jtag  # or zc706-nist_qc2-jtag or zc706-nist_clock-sd or etc
+nix build .#zc706-nist_clock-jtag  # or zc706-nist_qc2-jtag or zc706-nist_clock_satellite-jtag etc.
 ./remote_run.sh
 ```
-Run ``nix flake show`` to see all valid build targets. Targets suffixed with ``-jtag`` produce separate firmware and gateware files, intended for use in booting via JTAG server/Ethernet, e.g. ``./remote_run.sh -i`` with a remote JTAG server. Targets suffixed with ``-sd`` will produce ``boot.bin`` file suitable for SD card boot. ``-firmware`` and ``-gateware`` respectively build firmware and gateware only.
+Impure incremental build and execution on a remote JTAG server:
 The Kasli-SoC target requires a system description file as input. See ARTIQ manual for exact instructions or use incremental build.
 **Impure incremental build:**
 For boards with fixed variants, i.e. ZC706, etc. :
 ```shell
 nix develop
 cd src
-gateware/<board>.py -g ../build/gateware -V <variant> # gateware
+gateware/zc706.py -g ../build/gateware -V <variant> # build gateware
-make GWARGS="-V <variant>" <runtime/satman>    # firmware
+make GWARGS="-V <variant>" <runtime/satman>    # build firmware
-```
+cd ..
-
+./remote_run.sh -i
 For boards with system descriptions, i.e. Kasli-SoC, etc. :
 ```shell
 nix develop
 cd src
 gateware/<board>.py -g ../build/gateware <description.json> # gateware
 make TARGET=<board> GWARGS="path/to/description.json" <runtime/satman> # firmware
 ```
 ``szl.elf`` can be obtained with:
 ```shell
 nix build git+https://git.m-labs.hk/m-labs/zynq-rs#<board>-szl
 ```
 To generate ``boot.bin`` use ``mkbootimage``, e.g.:
 ```shell
 echo "the_ROM_image:
    {
        [bootloader]result/szl.elf
        gateware/top.bit
        firmware/armv7-none-eabihf/release/<runtime/satman>
    }
    EOF" >> boot.bif
 mkbootimage boot.bif boot.bin
 ```
 Notes:
 - The impure build process is also compatible with non-Nix systems.
 - When calling make, you need to specify both the variant and firmware type.
 - Firmware type must be either ``runtime`` for DRTIO-less or DRTIO master variants, or ``satman`` for DRTIO satellite.
- If the board is connected to the local machine by JTAG, use the ``local_run.sh`` script.
+- If the board is connected to the local machine, use the ``local_run.sh`` script.
 - A known Xilinx hardware bug prevents repeatedly loading the bootloader over JTAG without a POR reset. If booting over JTAG, install a jumper on ``PS_POR_B`` and use the POR reset script [here](https://git.m-labs.hk/M-Labs/zynq-rs/src/branch/master/kasli_soc_por.py).
 Pre-Commit Hooks
 ----------------
--- a/examples/ebaz4205/device_db.py
+++ b/examples/ebaz4205/device_db.py
@ -53,21 +53,13 @@ device_db = {
    },
 }
 # TTLs starting at RTIO channel 2, ending at RTIO channel 15
 for i in range(2, 16):
    device_db["ttl" + str(i)] = {
        "type": "local",
        "module": "artiq.coredevice.ttl",
        "class": "TTLInOut",
        "arguments": {"channel": i},
    }
 device_db.update(
    spi0={
        "type": "local",
        "module": "artiq.coredevice.spi2",
        "class": "SPIMaster",
-        "arguments": {"channel": 16},
+        "arguments": {"channel": 2},
    },
    dds0={
        "type": "local",
--- a/flake.lock
+++ b/flake.lock
@ -11,11 +11,11 @@
        "src-pythonparser": "src-pythonparser"
      },
      "locked": {
-        "lastModified": 1734418848,
+        "lastModified": 1727765117,
-        "narHash": "sha256-FiK84edtdmpJ3FUA58XAUmDDp4oVPgupmf1CcgJ6rC0=",
+        "narHash": "sha256-P4PgnsXNL4kXjSAhRpXzkq17j8bEaJAqNLSH2Vt+DY0=",
        "ref": "refs/heads/master",
-        "rev": "366bb0fc59dbe4d5f544908b0f3e31f8eb19f7c1",
+        "rev": "333623e24bdec00783bc89c1e8b6b49a74bc9e1c",
-        "revCount": 9121,
+        "revCount": 9020,
        "type": "git",
        "url": "https://github.com/m-labs/artiq.git"
      },
@ -68,13 +68,45 @@
        "type": "github"
      }
    },
    "mozilla-overlay": {
      "flake": false,
      "locked": {
        "lastModified": 1704373101,
        "narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
        "owner": "mozilla",
        "repo": "nixpkgs-mozilla",
        "rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
        "type": "github"
      },
      "original": {
        "owner": "mozilla",
        "repo": "nixpkgs-mozilla",
        "type": "github"
      }
    },
    "mozilla-overlay_2": {
      "flake": false,
      "locked": {
        "lastModified": 1704373101,
        "narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
        "owner": "mozilla",
        "repo": "nixpkgs-mozilla",
        "rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
        "type": "github"
      },
      "original": {
        "owner": "mozilla",
        "repo": "nixpkgs-mozilla",
        "type": "github"
      }
    },
    "nixpkgs": {
      "locked": {
-        "lastModified": 1733940404,
+        "lastModified": 1727348695,
-        "narHash": "sha256-Pj39hSoUA86ZePPF/UXiYHHM7hMIkios8TYG29kQT4g=",
+        "narHash": "sha256-J+PeFKSDV+pHL7ukkfpVzCOO7mBSrrpJ3svwBFABbhI=",
        "owner": "NixOS",
        "repo": "nixpkgs",
-        "rev": "5d67ea6b4b63378b9c13be21e2ec9d1afc921713",
+        "rev": "1925c603f17fc89f4c8f6bf6f631a802ad85d784",
        "type": "github"
      },
      "original": {
@ -87,6 +119,7 @@
    "root": {
      "inputs": {
        "artiq": "artiq",
        "mozilla-overlay": "mozilla-overlay",
        "zynq-rs": "zynq-rs"
      }
    },
@ -112,28 +145,6 @@
        "type": "github"
      }
    },
    "rust-overlay_2": {
      "inputs": {
        "nixpkgs": [
          "zynq-rs",
          "nixpkgs"
        ]
      },
      "locked": {
        "lastModified": 1719454714,
        "narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
        "owner": "oxalica",
        "repo": "rust-overlay",
        "rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
        "type": "github"
      },
      "original": {
        "owner": "oxalica",
        "ref": "snapshot/2024-08-01",
        "repo": "rust-overlay",
        "type": "github"
      }
    },
    "sipyco": {
      "inputs": {
        "nixpkgs": [
@ -142,11 +153,11 @@
        ]
      },
      "locked": {
-        "lastModified": 1734267097,
+        "lastModified": 1724921939,
-        "narHash": "sha256-aWg7XDiOlWnkXfDbKrBn9ITR46/JXfndvYHxFJ1vN78=",
+        "narHash": "sha256-/S5iip1LHLiCP2VY7PwClDteP9ZMRZvzzKR1LZuV3fs=",
        "owner": "m-labs",
        "repo": "sipyco",
-        "rev": "430978ada3fefe32de01f1b884b3031e48aaef96",
+        "rev": "32ddd78ff3641b75054793ea0d5681c951766754",
        "type": "github"
      },
      "original": {
@ -174,11 +185,11 @@
    "src-misoc": {
      "flake": false,
      "locked": {
-        "lastModified": 1729234629,
+        "lastModified": 1715647536,
-        "narHash": "sha256-TLsTCXV5AC2xh+bS7EhBVBKqdqIU3eKrnlWcFF9LtAM=",
+        "narHash": "sha256-q+USDcaKHABwW56Jzq8u94iGPWlyLXMyVt0j/Gyg+IE=",
        "ref": "refs/heads/master",
-        "rev": "6085a312bca26adeca6584e37d08c8ba2e1d6e38",
+        "rev": "fea9de558c730bc394a5936094ae95bb9d6fa726",
-        "revCount": 2460,
+        "revCount": 2455,
        "submodules": true,
        "type": "git",
        "url": "https://github.com/m-labs/misoc.git"
@ -222,18 +233,18 @@
    },
    "zynq-rs": {
      "inputs": {
        "mozilla-overlay": "mozilla-overlay_2",
        "nixpkgs": [
          "artiq",
          "nixpkgs"
-        ],
+        ]
        "rust-overlay": "rust-overlay_2"
      },
      "locked": {
-        "lastModified": 1734668221,
+        "lastModified": 1728110308,
-        "narHash": "sha256-X0U2yPmlsD3VLBZQyfWv8qw04Qn0qFWIONJUPPigB0U=",
+        "narHash": "sha256-MAoFbcDgr+ZjptFCWfthK+tTnR1NcfuO6tvYhNM2Pwo=",
        "ref": "refs/heads/master",
-        "rev": "213529cf7a50aa1b2d9ffdf575e3e38202ff9bd6",
+        "rev": "cc20478d91e30e1448a4304df7003caed2981b71",
-        "revCount": 666,
+        "revCount": 651,
        "type": "git",
        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
      },
--- a/flake.nix
+++ b/flake.nix
@ -2,15 +2,16 @@
  description = "ARTIQ port to the Zynq-7000 platform";
  inputs.artiq.url = git+https://github.com/m-labs/artiq.git;
  inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };
  inputs.zynq-rs.url = git+https://git.m-labs.hk/m-labs/zynq-rs;
  inputs.zynq-rs.inputs.nixpkgs.follows = "artiq/nixpkgs";
-  outputs = { self, zynq-rs, artiq }:
+  outputs = { self, mozilla-overlay, zynq-rs, artiq }:
  let
-    pkgs = import artiq.inputs.nixpkgs { system = "x86_64-linux"; overlays = [ (import zynq-rs.inputs.rust-overlay) ]; };
+    pkgs = import artiq.inputs.nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) ]; };
    zynqpkgs = zynq-rs.packages.x86_64-linux;
    artiqpkgs = artiq.packages.x86_64-linux;
-    zynqRev = self.sourceInfo.rev or "unknown";
+    llvmPackages_11 = zynq-rs.llvmPackages_11;
    rust = zynq-rs.rust;
    rustPlatform = zynq-rs.rustPlatform;
@ -125,9 +126,7 @@
          lockFile = src/Cargo.lock;
          outputHashes = {
              "tar-no-std-0.1.8" = "sha256-xm17108v4smXOqxdLvHl9CxTCJslmeogjm4Y87IXFuM=";
-              "nalgebra-0.32.6" = "sha256-ZbQQZbM3A5cJ4QbujtUxkrI0/qGlI4UzfahtyQnvMZA=";
+              "nalgebra-0.32.6" = "sha256-L/YudkVOtfGYoNQKBD7LMk/sMYgRDzPDdpGL5rO7G2I=";
              "core_io-0.1.0" = "sha256-0HINFWRiJx8pjMgUOL/CS336ih7SENSRh3Kah9LPRrw=";
              "fatfs-0.3.6" = "sha256-Nz9hCq/1YgSXF8ltJ5ZawV0Hc8WV44KNK0tJdVnNb4U=";
            };
        };
@ -135,13 +134,12 @@
          pkgs.gnumake
          (pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
          zynqpkgs.cargo-xbuild
-          pkgs.llvmPackages_13.llvm
+          llvmPackages_11.llvm
-          pkgs.llvmPackages_13.clang-unwrapped
+          llvmPackages_11.clang-unwrapped
        ];
        buildPhase = ''
          export ZYNQ_REV=${zynqRev}
          export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
-          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_13.clang-unwrapped.lib}/lib/clang/13.0.1/include"
+          export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
          export CARGO_HOME=$(mktemp -d cargo-home.XXX)
          export ZYNQ_RS=${zynq-rs}
          make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
@ -167,7 +165,6 @@
          ];
        }
        ''
          export ZYNQ_REV=${zynqRev}
          python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
          mkdir -p $out $out/nix-support
          cp build/top.bit $out
@ -376,8 +373,8 @@
      name = "artiq-zynq-dev-shell";
      buildInputs = with pkgs; [
        rust
-        llvmPackages_13.llvm
+        llvmPackages_11.llvm
-        llvmPackages_13.clang-unwrapped
+        llvmPackages_11.clang-unwrapped
        gnumake
        cacert
        zynqpkgs.cargo-xbuild
@ -390,9 +387,8 @@
        binutils-arm
        pre-commit
      ];
      ZYNQ_REV="${zynqRev}";
      XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
-      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_13.clang-unwrapped.lib}/lib/clang/13.0.1/include";
+      CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
      ZYNQ_RS = "${zynq-rs}";
      OPENOCD_ZYNQ = "${zynq-rs}/openocd";
      SZL = "${zynqpkgs.szl}";
--- a/src/Cargo.lock
+++ b/src/Cargo.lock
@ -58,9 +58,9 @@ version = "0.0.0"
 [[package]]
 name = "byteorder"
-version = "1.3.0"
+version = "1.4.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "60f0b0d4c0a382d2734228fd12b5a6b5dac185c60e938026fd31b265b94f9bd2"
+checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
 [[package]]
 name = "cc"
@ -82,14 +82,18 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 [[package]]
 name = "compiler_builtins"
-version = "0.1.49"
+version = "0.1.39"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "20b1438ef42c655665a8ab2c1c6d605a305f031d38d9be689ddfef41a20f3aa2"
+checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
 [[package]]
 name = "core_io"
-version = "0.1.0"
+version = "0.1.20210325"
-source = "git+https://git.m-labs.hk/M-Labs/rs-core_io.git?rev=e9d3edf027#e9d3edf0272502b0dd6c26e8a4869c2912657615"
+source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
 dependencies = [
 "rustc_version",
 ]
 [[package]]
 name = "crc"
@ -137,8 +141,9 @@ dependencies = [
 [[package]]
 name = "fatfs"
-version = "0.3.6"
+version = "0.3.5"
-source = "git+https://git.m-labs.hk/M-Labs/rust-fatfs.git?rev=4b5e420084#4b5e420084fd1c4a9c105680b687523909b6469c"
+source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
 dependencies = [
 "bitflags",
 "byteorder",
@ -368,9 +373,9 @@ checksum = "822add9edb1860698b79522510da17bef885171f75aa395cff099d770c609c24"
 [[package]]
 name = "log"
-version = "0.4.14"
+version = "0.4.17"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "51b9bbe6c47d51fc3e1a9b945965946b4c44142ab8792c50835a980d362c2710"
+checksum = "abb12e687cfb44aa40f41fc3978ef76448f9b6038cad6aef4259d3c095a2382e"
 dependencies = [
 "cfg-if 1.0.0",
 ]
@ -390,7 +395,7 @@ checksum = "c75de51135344a4f8ed3cfe2720dc27736f7711989703a0b43aadf3753c55577"
 [[package]]
 name = "nalgebra"
 version = "0.32.6"
-source = "git+https://git.m-labs.hk/M-Labs/nalgebra.git?rev=ad42410ab0#ad42410ab0abb014229e3ff6bc6ccd39ca92d5d1"
+source = "git+https://git.m-labs.hk/M-Labs/nalgebra.git?rev=dd00f9b#dd00f9b46046e0b931d1b470166db02fd29591be"
 dependencies = [
 "approx",
 "num-complex",
@ -515,7 +520,6 @@ dependencies = [
 "build_zynq",
 "byteorder",
 "core_io",
 "crc",
 "cslice",
 "dwarf",
 "dyld",
@ -541,14 +545,21 @@ dependencies = [
 "void",
 ]
 [[package]]
 name = "rustc_version"
 version = "0.1.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
 dependencies = [
 "semver",
 ]
 [[package]]
 name = "satman"
 version = "0.0.0"
 dependencies = [
 "build_zynq",
 "byteorder",
 "core_io",
 "crc",
 "cslice",
 "embedded-hal",
 "io",
@ -565,6 +576,12 @@ dependencies = [
 "unwind",
 ]
 [[package]]
 name = "semver"
 version = "0.1.20"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
 [[package]]
 name = "simba"
 version = "0.8.0"
--- a/src/armv7-none-eabihf.json
+++ b/src/armv7-none-eabihf.json
@ -1,4 +1,12 @@
 {
  "abi-blacklist": [
    "stdcall",
    "fastcall",
    "vectorcall",
    "thiscall",
    "win64",
    "sysv64"
  ],
  "arch": "arm",
  "data-layout": "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",
  "emit-debug-gdb-scripts": false,
@ -13,6 +21,7 @@
  "os": "none",
  "panic-strategy": "abort",
  "requires-uwtable": true,
  "force-unwind-tables": "yes",
  "relocation-model": "static",
  "target-c-int-width": "32",
  "target-endian": "little",
--- a/src/gateware/config.py
+++ b/src/gateware/config.py
@ -1,15 +1,5 @@
 import os
 from artiq._version import get_version
 from misoc.integration import cpu_interface
 def generate_ident(variant):
    return "{}+{};{}".format(
        get_version().split(".")[0],
        os.getenv("ZYNQ_REV", default="unknown")[:8],
        variant,
    )
 def write_csr_file(soc, filename):
    with open(filename, "w") as f:
        f.write(cpu_interface.get_csr_rust(
--- a/src/gateware/ebaz4205.py
+++ b/src/gateware/ebaz4205.py
@ -5,9 +5,9 @@ import argparse
 import analyzer
 import dma
 from artiq.gateware import rtio
-from artiq.gateware.rtio.phy import spi2, ttl_simple
+from artiq.gateware.rtio.phy import dds, spi2, ttl_simple
 from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
-from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 from migen import *
 from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
 from migen.build.platforms import ebaz4205
@ -91,17 +91,6 @@ _spi = [
 ]
 # Connector DATA1
 def _create_ttl():
    _ttl = []
    for idx, elem in enumerate([x for x in range(5, 21) if x not in (10, 12)]):
        _ttl.append(
            ("ttl", idx, Pins("DATA1:DATA1-{}".format(elem)), IOStandard("LVCMOS33")),
        )
    return _ttl
 class EBAZ4205(SoCCore):
    def __init__(self, rtio_clk=125e6, acpki=False):
        self.acpki = acpki
@ -116,7 +105,6 @@ class EBAZ4205(SoCCore):
        platform.add_extension(_ddr)
        platform.add_extension(_i2c)
        platform.add_extension(_spi)
        platform.add_extension(_create_ttl())
        gmii = platform.request("gmii")
        platform.add_period_constraint(gmii.rx_clk, 10)
@ -125,7 +113,7 @@ class EBAZ4205(SoCCore):
            "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
        )
-        ident = generate_ident(self.__class__.__name__)
+        ident = self.__class__.__name__
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
@ -192,13 +180,6 @@ class EBAZ4205(SoCCore):
            self.submodules += phy
            self.rtio_channels.append(rtio.Channel.from_phy(phy))
        for i in range(14):
            print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
            ttl = self.platform.request("ttl", i)
            phy = ttl_simple.InOut(ttl)
            self.submodules += phy
            self.rtio_channels.append(rtio.Channel.from_phy(phy))
        print("SPI at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
        spi_phy = spi2.SPIMaster(platform.request("spi"))
        self.submodules += spi_phy
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@ -24,10 +24,10 @@ from artiq.gateware.wrpll import wrpll
 import dma
 import analyzer
-import acpki as acpki_lib
+import acpki
 import drtio_aux_controller
 import zynq_clocking
-from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 eem_iostandard_dict = {
     0: "LVDS_25",
@ -115,7 +115,7 @@ class GenericStandalone(SoCCore):
        platform.toolchain.bitstream_commands.extend([
            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
        ])
-        ident = generate_ident(description["variant"])
+        ident = description["variant"]
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -184,10 +184,10 @@ class GenericStandalone(SoCCore):
        if self.acpki:
            self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                             bus=self.ps7.s_axi_acp,
+                                                         bus=self.ps7.s_axi_acp,
-                                                             user=self.ps7.s_axi_acp_user,
+                                                         user=self.ps7.s_axi_acp_user,
-                                                             evento=self.ps7.event.o)
+                                                         evento=self.ps7.event.o)
            self.csr_devices.append("rtio")
        else:
            self.config["KI_IMPL"] = "csr"
@ -229,7 +229,7 @@ class GenericMaster(SoCCore):
        platform.toolchain.bitstream_commands.extend([
            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
        ])
-        ident = generate_ident(description["variant"])
+        ident = description["variant"]
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -349,10 +349,10 @@ class GenericMaster(SoCCore):
        if self.acpki:
            self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                             bus=self.ps7.s_axi_acp,
+                                                         bus=self.ps7.s_axi_acp,
-                                                             user=self.ps7.s_axi_acp_user,
+                                                         user=self.ps7.s_axi_acp_user,
-                                                             evento=self.ps7.event.o)
+                                                         evento=self.ps7.event.o)
            self.csr_devices.append("rtio")
        else:
            self.config["KI_IMPL"] = "csr"
@ -438,7 +438,7 @@ class GenericSatellite(SoCCore):
        platform.toolchain.bitstream_commands.extend([
            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
        ])
-        ident = generate_ident(description["variant"])
+        ident = description["variant"]
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -544,10 +544,10 @@ class GenericSatellite(SoCCore):
        if self.acpki:
            self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                             bus=self.ps7.s_axi_acp,
+                                                         bus=self.ps7.s_axi_acp,
-                                                             user=self.ps7.s_axi_acp_user,
+                                                         user=self.ps7.s_axi_acp_user,
-                                                             evento=self.ps7.event.o)
+                                                         evento=self.ps7.event.o)
            self.csr_devices.append("rtio")
        else:
            self.config["KI_IMPL"] = "csr"
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@ -25,7 +25,7 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
-from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 class SMAClkinForward(Module):
    def __init__(self, platform):
@ -130,7 +130,7 @@ class ZC706(SoCCore):
        platform = zc706.Platform()
        prepare_zc706_platform(platform)
-        ident = generate_ident(self.__class__.__name__)
+        ident = self.__class__.__name__
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -203,7 +203,7 @@ class _MasterBase(SoCCore):
        platform = zc706.Platform()
        prepare_zc706_platform(platform)
-        ident = generate_ident(self.__class__.__name__)
+        ident = self.__class__.__name__
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -344,7 +344,7 @@ class _SatelliteBase(SoCCore):
        platform = zc706.Platform()
        prepare_zc706_platform(platform)
-        ident = generate_ident(self.__class__.__name__)
+        ident = self.__class__.__name__
        if self.acpki:
            ident = "acpki_" + ident
        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
--- a/src/libboard_artiq/Cargo.toml.tpl
+++ b/src/libboard_artiq/Cargo.toml.tpl
@ -20,7 +20,7 @@ build_zynq = { path = "../libbuild_zynq" }
 log = "0.4"
 log_buffer = { version = "1.2" }
 crc = { version = "1.7", default-features = false }
-core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
+core_io = { version = "0.1", features = ["collections"] }
 embedded-hal = "0.2"
 nb = "1.0"
 void = { version = "1", default-features = false }
--- a/src/libboard_artiq/src/drtio_eem.rs
+++ b/src/libboard_artiq/src/drtio_eem.rs
@ -185,24 +185,6 @@ unsafe fn align_comma(timer: &mut GlobalTimer) {
    }
 }
 pub unsafe fn align_wordslip(timer: &mut GlobalTimer, trx_no: u8) -> bool {
    pl::csr::eem_transceiver::transceiver_sel_write(trx_no);
    for slip in 0..=1 {
        pl::csr::eem_transceiver::wordslip_write(slip as u8);
        timer.delay_us(1);
        pl::csr::eem_transceiver::comma_align_reset_write(1);
        timer.delay_us(100);
        if pl::csr::eem_transceiver::comma_read() == 1 {
            debug!("comma alignment completed with {} wordslip", slip);
            return true;
        }
    }
    false
 }
 pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
    for trx_no in 0..pl::csr::CONFIG_EEM_DRTIO_COUNT {
        unsafe {
@ -240,6 +222,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
        unsafe {
            align_comma(timer);
            pl::csr::eem_transceiver::rx_ready_write(1);
        }
    }
 }
--- a/src/libboard_artiq/src/drtioaux.rs
+++ b/src/libboard_artiq/src/drtioaux.rs
@ -6,7 +6,7 @@ use io::{proto::{ProtoRead, ProtoWrite},
         Cursor};
 use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
-pub use crate::drtioaux_proto::{Packet, MAX_PACKET};
+pub use crate::drtioaux_proto::Packet;
 use crate::{drtioaux_proto::Error as ProtocolError, mem::mem::DRTIOAUX_MEM, pl::csr::DRTIOAUX};
 #[derive(Debug)]
@ -35,15 +35,6 @@ impl From<IoError> for Error {
    }
 }
 pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) {
    // fix for artiq-zynq#344
    unsafe {
        for i in 0..(len / 4) {
            *dst.offset(i) = *src.offset(i);
        }
    }
 }
 pub fn reset(linkno: u8) {
    let linkno = linkno as usize;
    unsafe {
@ -124,9 +115,7 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
    unsafe {
        while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
        let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
-        let mut buf: [u8; MAX_PACKET] = [0; MAX_PACKET];
+        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
        let len = f(&mut buf)?;
        copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
        (DRTIOAUX[linkno].aux_tx_write)(1);
        Ok(())
--- a/src/libboard_artiq/src/drtioaux_async.rs
+++ b/src/libboard_artiq/src/drtioaux_async.rs
@ -9,8 +9,8 @@ use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
 use nb;
 use void::Void;
-pub use crate::drtioaux_proto::{Packet, MAX_PACKET};
+pub use crate::drtioaux_proto::Packet;
-use crate::{drtioaux::{copy_work_buffer, has_rx_error, Error},
+use crate::{drtioaux::{has_rx_error, Error},
            mem::mem::DRTIOAUX_MEM,
            pl::csr::DRTIOAUX};
@ -102,9 +102,7 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
    unsafe {
        let _ = block_async!(tx_ready(linkno)).await;
        let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
-        let mut buf: [u8; MAX_PACKET] = [0; MAX_PACKET];
+        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
        let len = f(&mut buf)?;
        copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
        (DRTIOAUX[linkno].aux_tx_write)(1);
        Ok(())
--- a/src/libboard_artiq/src/drtioaux_proto.rs
+++ b/src/libboard_artiq/src/drtioaux_proto.rs
@ -1,12 +1,11 @@
 use core_io::{Error as IoError, Read, Write};
 use io::proto::{ProtoRead, ProtoWrite};
-pub const MAX_PACKET: usize = 1024;
+const MAX_PACKET: usize = 1024;
 // maximum size of arbitrary payloads
 // used by satellite -> master analyzer, subkernel exceptions
-pub const SAT_PAYLOAD_MAX_SIZE: usize = /*max size*/
+pub const SAT_PAYLOAD_MAX_SIZE: usize  = /*max size*/MAX_PACKET - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
    MAX_PACKET - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
 // used by DDMA, subkernel program data (need to provide extra ID and destination)
 pub const MASTER_PAYLOAD_MAX_SIZE: usize = SAT_PAYLOAD_MAX_SIZE - /*source*/1 - /*destination*/1 - /*ID*/4;
@ -289,77 +288,6 @@ pub enum Packet {
    SubkernelMessageAck {
        destination: u8,
    },
    CoreMgmtGetLogRequest {
        destination: u8,
        clear: bool,
    },
    CoreMgmtClearLogRequest {
        destination: u8,
    },
    CoreMgmtSetLogLevelRequest {
        destination: u8,
        log_level: u8,
    },
    CoreMgmtSetUartLogLevelRequest {
        destination: u8,
        log_level: u8,
    },
    CoreMgmtConfigReadRequest {
        destination: u8,
        length: u16,
        key: [u8; MASTER_PAYLOAD_MAX_SIZE],
    },
    CoreMgmtConfigReadContinue {
        destination: u8,
    },
    CoreMgmtConfigWriteRequest {
        destination: u8,
        last: bool,
        length: u16,
        data: [u8; MASTER_PAYLOAD_MAX_SIZE],
    },
    CoreMgmtConfigRemoveRequest {
        destination: u8,
        length: u16,
        key: [u8; MASTER_PAYLOAD_MAX_SIZE],
    },
    CoreMgmtConfigEraseRequest {
        destination: u8,
    },
    CoreMgmtRebootRequest {
        destination: u8,
    },
    CoreMgmtAllocatorDebugRequest {
        destination: u8,
    },
    CoreMgmtFlashRequest {
        destination: u8,
        payload_length: u32,
    },
    CoreMgmtFlashAddDataRequest {
        destination: u8,
        last: bool,
        length: u16,
        data: [u8; MASTER_PAYLOAD_MAX_SIZE],
    },
    CoreMgmtDropLinkAck {
        destination: u8,
    },
    CoreMgmtDropLink,
    CoreMgmtGetLogReply {
        last: bool,
        length: u16,
        data: [u8; SAT_PAYLOAD_MAX_SIZE],
    },
    CoreMgmtConfigReadReply {
        last: bool,
        length: u16,
        value: [u8; SAT_PAYLOAD_MAX_SIZE],
    },
    CoreMgmtReply {
        succeeded: bool,
    },
 }
 impl Packet {
@ -637,115 +565,6 @@ impl Packet {
                destination: reader.read_u8()?,
            },
            0xd0 => Packet::CoreMgmtGetLogRequest {
                destination: reader.read_u8()?,
                clear: reader.read_bool()?,
            },
            0xd1 => Packet::CoreMgmtClearLogRequest {
                destination: reader.read_u8()?,
            },
            0xd2 => Packet::CoreMgmtSetLogLevelRequest {
                destination: reader.read_u8()?,
                log_level: reader.read_u8()?,
            },
            0xd3 => Packet::CoreMgmtSetUartLogLevelRequest {
                destination: reader.read_u8()?,
                log_level: reader.read_u8()?,
            },
            0xd4 => {
                let destination = reader.read_u8()?;
                let length = reader.read_u16()?;
                let mut key: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
                reader.read_exact(&mut key[0..length as usize])?;
                Packet::CoreMgmtConfigReadRequest {
                    destination: destination,
                    length: length,
                    key: key,
                }
            }
            0xd5 => Packet::CoreMgmtConfigReadContinue {
                destination: reader.read_u8()?,
            },
            0xd6 => {
                let destination = reader.read_u8()?;
                let last = reader.read_bool()?;
                let length = reader.read_u16()?;
                let mut data: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
                reader.read_exact(&mut data[0..length as usize])?;
                Packet::CoreMgmtConfigWriteRequest {
                    destination: destination,
                    last: last,
                    length: length,
                    data: data,
                }
            }
            0xd7 => {
                let destination = reader.read_u8()?;
                let length = reader.read_u16()?;
                let mut key: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
                reader.read_exact(&mut key[0..length as usize])?;
                Packet::CoreMgmtConfigRemoveRequest {
                    destination: destination,
                    length: length,
                    key: key,
                }
            }
            0xd8 => Packet::CoreMgmtConfigEraseRequest {
                destination: reader.read_u8()?,
            },
            0xd9 => Packet::CoreMgmtRebootRequest {
                destination: reader.read_u8()?,
            },
            0xda => Packet::CoreMgmtAllocatorDebugRequest {
                destination: reader.read_u8()?,
            },
            0xdb => Packet::CoreMgmtFlashRequest {
                destination: reader.read_u8()?,
                payload_length: reader.read_u32()?,
            },
            0xdc => {
                let destination = reader.read_u8()?;
                let last = reader.read_bool()?;
                let length = reader.read_u16()?;
                let mut data: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
                reader.read_exact(&mut data[0..length as usize])?;
                Packet::CoreMgmtFlashAddDataRequest {
                    destination: destination,
                    last: last,
                    length: length,
                    data: data,
                }
            }
            0xdd => Packet::CoreMgmtDropLinkAck {
                destination: reader.read_u8()?,
            },
            0xde => Packet::CoreMgmtDropLink,
            0xdf => {
                let last = reader.read_bool()?;
                let length = reader.read_u16()?;
                let mut data: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
                reader.read_exact(&mut data[0..length as usize])?;
                Packet::CoreMgmtGetLogReply {
                    last: last,
                    length: length,
                    data: data,
                }
            }
            0xe0 => {
                let last = reader.read_bool()?;
                let length = reader.read_u16()?;
                let mut value: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
                reader.read_exact(&mut value[0..length as usize])?;
                Packet::CoreMgmtConfigReadReply {
                    last: last,
                    length: length,
                    value: value,
                }
            }
            0xe1 => Packet::CoreMgmtReply {
                succeeded: reader.read_bool()?,
            },
            ty => return Err(Error::UnknownPacket(ty)),
        })
    }
@ -1123,115 +942,6 @@ impl Packet {
                writer.write_u8(0xcc)?;
                writer.write_u8(destination)?;
            }
            Packet::CoreMgmtGetLogRequest { destination, clear } => {
                writer.write_u8(0xd0)?;
                writer.write_u8(destination)?;
                writer.write_bool(clear)?;
            }
            Packet::CoreMgmtClearLogRequest { destination } => {
                writer.write_u8(0xd1)?;
                writer.write_u8(destination)?;
            }
            Packet::CoreMgmtSetLogLevelRequest { destination, log_level } => {
                writer.write_u8(0xd2)?;
                writer.write_u8(destination)?;
                writer.write_u8(log_level)?;
            }
            Packet::CoreMgmtSetUartLogLevelRequest { destination, log_level } => {
                writer.write_u8(0xd3)?;
                writer.write_u8(destination)?;
                writer.write_u8(log_level)?;
            }
            Packet::CoreMgmtConfigReadRequest {
                destination,
                length,
                key,
            } => {
                writer.write_u8(0xd4)?;
                writer.write_u8(destination)?;
                writer.write_u16(length)?;
                writer.write_all(&key[0..length as usize])?;
            }
            Packet::CoreMgmtConfigReadContinue { destination } => {
                writer.write_u8(0xd5)?;
                writer.write_u8(destination)?;
            }
            Packet::CoreMgmtConfigWriteRequest {
                destination,
                last,
                length,
                data,
            } => {
                writer.write_u8(0xd6)?;
                writer.write_u8(destination)?;
                writer.write_bool(last)?;
                writer.write_u16(length)?;
                writer.write_all(&data[0..length as usize])?;
            }
            Packet::CoreMgmtConfigRemoveRequest {
                destination,
                length,
                key,
            } => {
                writer.write_u8(0xd7)?;
                writer.write_u8(destination)?;
                writer.write_u16(length)?;
                writer.write_all(&key[0..length as usize])?;
            }
            Packet::CoreMgmtConfigEraseRequest { destination } => {
                writer.write_u8(0xd8)?;
                writer.write_u8(destination)?;
            }
            Packet::CoreMgmtRebootRequest { destination } => {
                writer.write_u8(0xd9)?;
                writer.write_u8(destination)?;
            }
            Packet::CoreMgmtAllocatorDebugRequest { destination } => {
                writer.write_u8(0xda)?;
                writer.write_u8(destination)?;
            }
            Packet::CoreMgmtFlashRequest {
                destination,
                payload_length,
            } => {
                writer.write_u8(0xdb)?;
                writer.write_u8(destination)?;
                writer.write_u32(payload_length)?;
            }
            Packet::CoreMgmtFlashAddDataRequest {
                destination,
                last,
                length,
                data,
            } => {
                writer.write_u8(0xdc)?;
                writer.write_u8(destination)?;
                writer.write_bool(last)?;
                writer.write_u16(length)?;
                writer.write_all(&data[..length as usize])?;
            }
            Packet::CoreMgmtDropLinkAck { destination } => {
                writer.write_u8(0xdd)?;
                writer.write_u8(destination)?;
            }
            Packet::CoreMgmtDropLink => writer.write_u8(0xde)?,
            Packet::CoreMgmtGetLogReply { last, length, data } => {
                writer.write_u8(0xdf)?;
                writer.write_bool(last)?;
                writer.write_u16(length)?;
                writer.write_all(&data[0..length as usize])?;
            }
            Packet::CoreMgmtConfigReadReply { last, length, value } => {
                writer.write_u8(0xe0)?;
                writer.write_bool(last)?;
                writer.write_u16(length)?;
                writer.write_all(&value[0..length as usize])?;
            }
            Packet::CoreMgmtReply { succeeded } => {
                writer.write_u8(0xe1)?;
                writer.write_bool(succeeded)?;
            }
        }
        Ok(())
    }
@ -1268,9 +978,7 @@ impl Packet {
            | Packet::SubkernelLoadRunReply { .. }
            | Packet::SubkernelMessageAck { .. }
            | Packet::DmaPlaybackStatus { .. }
-            | Packet::SubkernelFinished { .. }
+            | Packet::SubkernelFinished { .. } => false,
            | Packet::CoreMgmtDropLinkAck { .. }
            | Packet::InjectionRequest { .. } => false,
            _ => true,
        }
    }
--- a/src/libdwarf/src/eh.rs
+++ b/src/libdwarf/src/eh.rs
@ -85,7 +85,10 @@ unsafe fn get_ttype_entry(
        encoding | DW_EH_PE_pcrel,
        ttype_base,
    )
-    .map(|v| (v != ttype_base).then(|| v as *const u8))
+    .map(|v| match v {
        ttype_base => None,
        ttype_entry => Some(ttype_entry as *const u8),
    })
 }
 pub unsafe fn find_eh_action(
--- a/src/libio/Cargo.toml.tpl
+++ b/src/libio/Cargo.toml.tpl
@ -8,7 +8,7 @@ name = "io"
 path = "lib.rs"
 [dependencies]
-core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
+core_io = { version = "0.1", features = ["collections"] }
 byteorder = { version = "1.0", default-features = false, optional = true }
 libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
--- a/src/libio/cursor.rs
+++ b/src/libio/cursor.rs
@ -1,6 +1,5 @@
 #[cfg(feature = "alloc")]
 use alloc::vec::Vec;
 use core::arch::asm;
 use core_io::{Error as IoError, Read, Write};
@ -48,9 +47,6 @@ impl<T: AsRef<[u8]>> Read for Cursor<T> {
        let len = buf.len().min(data.len());
        // ``copy_from_slice`` generates AXI bursts, use a regular loop instead
        for i in 0..len {
            unsafe {
                asm!("", options(preserves_flags, nostack, readonly));
            }
            buf[i] = data[i];
        }
        self.pos += len;
@ -63,9 +59,6 @@ impl Write for Cursor<&mut [u8]> {
        let data = &mut self.inner[self.pos..];
        let len = buf.len().min(data.len());
        for i in 0..len {
            unsafe {
                asm!("", options(preserves_flags, nostack, readonly));
            }
            data[i] = buf[i];
        }
        self.pos += len;
--- a/src/libio/lib.rs
+++ b/src/libio/lib.rs
@ -1,6 +1,5 @@
 #![no_std]
 #![feature(never_type)]
 #![feature(asm)]
 #[cfg(feature = "alloc")]
 extern crate alloc;
--- a/src/libksupport/Cargo.toml.tpl
+++ b/src/libksupport/Cargo.toml.tpl
@ -12,7 +12,7 @@ build_zynq = { path = "../libbuild_zynq" }
 cslice = "0.3"
 log = "0.4"
 nb = "0.1"
-core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
+core_io = { version = "0.1", features = ["collections"] }
 byteorder = { version = "1.3", default-features = false }
 void = { version = "1", default-features = false }
 log_buffer = { version = "1.2" }
@ -35,6 +35,6 @@ libboard_artiq = { path = "../libboard_artiq" }
 [dependencies.nalgebra]
 git = "https://git.m-labs.hk/M-Labs/nalgebra.git"
-rev = "ad42410ab0"
+rev = "dd00f9b"
 default-features = false
 features = ["libm", "alloc"]
--- a/src/libksupport/src/eh_artiq.rs
+++ b/src/libksupport/src/eh_artiq.rs
@ -96,35 +96,29 @@ struct ExceptionBuffer {
 }
 static mut EXCEPTION_BUFFER: ExceptionBuffer = ExceptionBuffer {
-    uw_exceptions: [const {
+    uw_exceptions: [uw::_Unwind_Exception {
-        uw::_Unwind_Exception {
+        exception_class: EXCEPTION_CLASS,
-            exception_class: EXCEPTION_CLASS,
+        exception_cleanup: cleanup,
-            exception_cleanup: cleanup,
+        private: [0; uw::unwinder_private_data_size],
            private: [0; uw::unwinder_private_data_size],
        }
    }; MAX_INFLIGHT_EXCEPTIONS],
    exceptions: [None; MAX_INFLIGHT_EXCEPTIONS + 1],
    exception_stack: [-1; MAX_INFLIGHT_EXCEPTIONS + 1],
    backtrace: [(0, 0); MAX_BACKTRACE_SIZE],
    backtrace_size: 0,
-    stack_pointers: [const {
+    stack_pointers: [StackPointerBacktrace {
-        StackPointerBacktrace {
+        stack_pointer: 0,
-            stack_pointer: 0,
+        initial_backtrace_size: 0,
-            initial_backtrace_size: 0,
+        current_backtrace_size: 0,
            current_backtrace_size: 0,
        }
    }; MAX_INFLIGHT_EXCEPTIONS + 1],
    exception_count: 0,
 };
 pub unsafe extern "C" fn reset_exception_buffer() {
    trace!("reset exception buffer");
-    EXCEPTION_BUFFER.uw_exceptions = [const {
+    EXCEPTION_BUFFER.uw_exceptions = [uw::_Unwind_Exception {
-        uw::_Unwind_Exception {
+        exception_class: EXCEPTION_CLASS,
-            exception_class: EXCEPTION_CLASS,
+        exception_cleanup: cleanup,
-            exception_cleanup: cleanup,
+        private: [0; uw::unwinder_private_data_size],
            private: [0; uw::unwinder_private_data_size],
        }
    }; MAX_INFLIGHT_EXCEPTIONS];
    EXCEPTION_BUFFER.exceptions = [None; MAX_INFLIGHT_EXCEPTIONS + 1];
    EXCEPTION_BUFFER.exception_stack = [-1; MAX_INFLIGHT_EXCEPTIONS + 1];
--- a/src/libksupport/src/kernel/dma.rs
+++ b/src/libksupport/src/kernel/dma.rs
@ -82,7 +82,7 @@ pub extern "C" fn dma_record_stop(duration: i64, enable_ddma: bool) {
 #[inline(always)]
 unsafe fn dma_record_output_prepare(timestamp: i64, target: i32, words: usize) {
    // See gateware/rtio/dma.py.
-    const HEADER_LENGTH: usize = /*length*/ 1 + /*channel*/3 + /*timestamp*/8 + /*address*/1;
+    const HEADER_LENGTH: usize = /*length*/1 + /*channel*/3 + /*timestamp*/8 + /*address*/1;
    let length = HEADER_LENGTH + /*data*/words * 4;
    let buffer = &mut RECORDER.as_mut().unwrap().buffer;
--- a/src/libksupport/src/lib.rs
+++ b/src/libksupport/src/lib.rs
@ -1,8 +1,7 @@
 #![no_std]
 #![allow(incomplete_features)]
 #![feature(c_variadic)]
 #![feature(const_btree_new)]
-#![feature(inline_const)]
+#![feature(const_in_array_repeat_expressions)]
 #![feature(naked_functions)]
 #![feature(asm)]
--- a/src/libunwind/lib.rs
+++ b/src/libunwind/lib.rs
@ -1,7 +1,7 @@
 #![no_std]
 #![feature(link_cfg)]
 #![feature(nll)]
-#![feature(c_unwind)]
+#![feature(unwind_attributes)]
 #![feature(static_nobundle)]
 #![cfg_attr(not(target_env = "msvc"), feature(libc))]
--- a/src/libunwind/libunwind.rs
+++ b/src/libunwind/libunwind.rs
@ -77,7 +77,8 @@ pub type _Unwind_Exception_Cleanup_Fn =
    all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux")),
    link(name = "unwind", kind = "static")
 )]
-extern "C-unwind" {
+extern "C" {
    #[unwind(allowed)]
    pub fn _Unwind_Resume(exception: *mut _Unwind_Exception) -> !;
    pub fn _Unwind_DeleteException(exception: *mut _Unwind_Exception);
    pub fn _Unwind_GetLanguageSpecificData(ctx: *mut _Unwind_Context) -> *mut c_void;
@ -225,7 +226,8 @@ if #[cfg(not(all(target_os = "ios", target_arch = "arm")))] {
    #[cfg_attr(all(feature = "llvm-libunwind",
                   any(target_os = "fuchsia", target_os = "linux")),
               link(name = "unwind", kind = "static"))]
-    extern "C-unwind" {
+    extern "C" {
        #[unwind(allowed)]
        pub fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwind_Reason_Code;
        pub fn _Unwind_Backtrace(trace: _Unwind_Trace_Fn,
                                 trace_argument: *mut c_void)
@ -236,7 +238,8 @@ if #[cfg(not(all(target_os = "ios", target_arch = "arm")))] {
    #[cfg_attr(all(feature = "llvm-libunwind",
                   any(target_os = "fuchsia", target_os = "linux")),
               link(name = "unwind", kind = "static"))]
-    extern "C-unwind" {
+    extern "C" {
        #[unwind(allowed)]
        pub fn _Unwind_SjLj_RaiseException(e: *mut _Unwind_Exception) -> _Unwind_Reason_Code;
    }
--- a/src/runtime/Cargo.toml.tpl
+++ b/src/runtime/Cargo.toml.tpl
@ -20,8 +20,7 @@ num-derive = "0.3"
 cslice = "0.3"
 log = "0.4"
 embedded-hal = "0.2"
-core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
+core_io = { version = "0.1", features = ["collections"] }
 crc = { version = "1.7", default-features = false }
 byteorder = { version = "1.3", default-features = false }
 void = { version = "1", default-features = false }
 futures = { version = "0.3", default-features = false, features = ["async-await"] }
@ -46,4 +45,4 @@ libboard_artiq = { path = "../libboard_artiq" }
 [dependencies.tar-no-std]
 git = "https://git.m-labs.hk/M-Labs/tar-no-std"
-rev = "2ab6dc5"
+rev = "2ab6dc5"
--- a/src/runtime/src/comms.rs
+++ b/src/runtime/src/comms.rs
@ -10,11 +10,15 @@ use io::Cursor;
 #[cfg(has_drtio)]
 use ksupport::rpc;
 use ksupport::{kernel, resolve_channel_name};
 #[cfg(has_drtio)]
 use libasync::delay;
 use libasync::{smoltcp::{Sockets, TcpStream},
               task};
 use libboard_artiq::drtio_routing;
 #[cfg(feature = "target_kasli_soc")]
 use libboard_zynq::error_led::ErrorLED;
 #[cfg(has_drtio)]
 use libboard_zynq::time::Milliseconds;
 use libboard_zynq::{self as zynq,
                    smoltcp::{self,
                              iface::{EthernetInterfaceBuilder, NeighborCache},
@ -781,15 +785,7 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
    let cfg = Rc::new(cfg);
    let restart_idle = Rc::new(Semaphore::new(1, 1));
-    mgmt::start(
+    mgmt::start(cfg.clone(), restart_idle.clone());
        cfg.clone(),
        restart_idle.clone(),
        Some(mgmt::DrtioContext(
            aux_mutex.clone(),
            drtio_routing_table.clone(),
            timer,
        )),
    );
    task::spawn(async move {
        let connection = Rc::new(Semaphore::new(1, 1));
@ -915,7 +911,7 @@ pub fn soft_panic_main(timer: GlobalTimer, cfg: Config) -> ! {
    Sockets::init(32);
    let dummy = Rc::new(Semaphore::new(0, 1));
-    mgmt::start(Rc::new(cfg), dummy, None);
+    mgmt::start(Rc::new(cfg), dummy);
    // getting eth settings disables the LED as it resets GPIO
    // need to re-enable it here
--- a/src/runtime/src/mgmt.rs
+++ b/src/runtime/src/mgmt.rs
--- a/src/runtime/src/rtio_clocking.rs
+++ b/src/runtime/src/rtio_clocking.rs
@ -12,7 +12,9 @@ use libboard_artiq::si549;
 use libboard_zynq::i2c::I2c;
 use libboard_zynq::timer::GlobalTimer;
 use libconfig::Config;
-use log::{info, warn};
+#[cfg(not(feature = "target_ebaz4205"))]
 use log::info;
 use log::warn;
 #[cfg(feature = "target_ebaz4205")]
 use {libboard_zynq::slcr, libregister::RegisterRW};
@ -414,32 +416,46 @@ fn get_si549_setting(clk: RtioClock) -> si549::FrequencySetting {
 fn set_fclk0_freq(clk: RtioClock, cfg: &Config) {
    let io_pll_freq: u32 = 1_000_000_000; // Hardcoded in zynq-rs
    let mut target_freq = 0;
    let mut divisor0 = 1u8;
    match clk {
        RtioClock::Int_100 => {
            target_freq = 100_000_000;
            divisor0 = 10;
        }
        RtioClock::Int_125 => {
            target_freq = 125_000_000;
            divisor0 = 8;
        }
-        _ => {
+        RtioClock::Int_150 => {
-            warn!("Unsupported RTIO Clock: '{:?}'", clk);
+            target_freq = 150_000_000;
-            return;
+        }
        _ => {}
    }
    let mut divisor0 = 1u8; // Start with divisor0 at 1
    let mut divisor1 = 1u8; // Default value for divisor1
    // Calculate the smallest valid divisor0 and divisor1 pair
    while divisor0 < 64 && io_pll_freq / u32::from(divisor0) > target_freq {
        divisor0 += 1;
    }
    // If divisor0 alone isn't enough, adjust divisor1 as well
    if io_pll_freq / (u32::from(divisor0) * u32::from(divisor1)) > target_freq {
        divisor1 += 1;
        divisor0 = 1;
        while divisor1 < 64 && io_pll_freq / (u32::from(divisor0) * u32::from(divisor1)) > target_freq {
            divisor1 += 1;
        }
    }
-    slcr::RegisterBlock::unlocked(|slcr| {
+    // Ensure the calculated divisors achieve the target frequency
-        slcr.fpga0_clk_ctrl.modify(|_, w| w.divisor0(divisor0));
+    if io_pll_freq / (u32::from(divisor0) * u32::from(divisor1)) == target_freq {
-    });
+        slcr::RegisterBlock::unlocked(|slcr| {
-
+            slcr.fpga0_clk_ctrl
-    info!(
+                .modify(|_, w| w.divisor0(divisor0).divisor1(divisor1));
-        "Set FCLK0 to {:.2} MHz (target: {} MHz).",
+        });
-        io_pll_freq as f64 / divisor0 as f64,
+    } else {
-        target_freq / 1_000_000
+        warn!("Could not set fclk0 for target frequency: '{:?}'", target_freq);
-    );
+    }
 }
 pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
@ -471,7 +487,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
    #[cfg(feature = "target_ebaz4205")]
    {
        match clk {
-            RtioClock::Int_100 | RtioClock::Int_125 => {
+            RtioClock::Int_100 | RtioClock::Int_125 | RtioClock::Int_150 => {
                set_fclk0_freq(clk, cfg);
            }
            _ => {} // Not set for external clocks
--- a/src/runtime/src/rtio_mgt.rs
+++ b/src/runtime/src/rtio_mgt.rs
@ -13,13 +13,9 @@ pub mod drtio {
    use core::fmt;
    use embedded_hal::blocking::delay::DelayMs;
    #[cfg(has_drtio_eem)]
    use embedded_hal::blocking::delay::DelayUs;
    use ksupport::{resolve_channel_name, ASYNC_ERROR_BUSY, ASYNC_ERROR_COLLISION, ASYNC_ERROR_SEQUENCE_ERROR,
                   SEEN_ASYNC_ERRORS};
    use libasync::{delay, task};
    #[cfg(has_drtio_eem)]
    use libboard_artiq::drtio_eem;
    use libboard_artiq::{drtioaux::Error as DrtioError,
                         drtioaux_async,
                         drtioaux_async::Packet,
@ -30,10 +26,6 @@ pub mod drtio {
    use super::*;
    use crate::{analyzer::remote_analyzer::RemoteBuffer, rtio_dma::remote_dma, subkernel};
    #[cfg(has_drtio_eem)]
    const DRTIO_EEM_LINKNOS: core::ops::Range<usize> =
        (csr::DRTIO.len() - csr::CONFIG_EEM_DRTIO_COUNT as usize)..csr::DRTIO.len();
    #[derive(Debug, PartialEq, Eq, Clone, Copy)]
    pub enum Error {
        Timeout,
@ -84,18 +76,8 @@ pub mod drtio {
        });
    }
-    async fn link_rx_up(linkno: u8, _timer: &mut GlobalTimer) -> bool {
+    async fn link_rx_up(linkno: u8) -> bool {
        let linkno = linkno as usize;
        #[cfg(has_drtio_eem)]
        if DRTIO_EEM_LINKNOS.contains(&linkno) {
            let eem_trx_no = linkno - DRTIO_EEM_LINKNOS.start;
            unsafe {
                csr::eem_transceiver::transceiver_sel_write(eem_trx_no as u8);
                csr::eem_transceiver::comma_align_reset_write(1);
            }
            _timer.delay_us(100);
            return unsafe { csr::eem_transceiver::comma_read() == 1 };
        }
        unsafe { (csr::DRTIO[linkno].rx_up_read)() == 1 }
    }
@ -170,8 +152,8 @@ pub mod drtio {
        }
    }
-    async fn recv_aux_timeout(linkno: u8, timeout: u64, mut timer: GlobalTimer) -> Result<Packet, Error> {
+    async fn recv_aux_timeout(linkno: u8, timeout: u64, timer: GlobalTimer) -> Result<Packet, Error> {
-        if !link_rx_up(linkno, &mut timer).await {
+        if !link_rx_up(linkno).await {
            return Err(Error::LinkDown);
        }
        match drtioaux_async::recv_timeout(linkno, Some(timeout), timer).await {
@ -186,9 +168,9 @@ pub mod drtio {
        linkno: u8,
        routing_table: &RoutingTable,
        request: &Packet,
-        mut timer: GlobalTimer,
+        timer: GlobalTimer,
    ) -> Result<Packet, Error> {
-        if !link_rx_up(linkno, &mut timer).await {
+        if !link_rx_up(linkno).await {
            return Err(Error::LinkDown);
        }
        let _lock = aux_mutex.async_lock().await;
@ -212,11 +194,11 @@ pub mod drtio {
        aux_mutex: &Rc<Mutex<bool>>,
        linkno: u8,
        routing_table: &RoutingTable,
-        mut timer: GlobalTimer,
+        timer: GlobalTimer,
    ) -> u32 {
        let mut count = 0;
        loop {
-            if !link_rx_up(linkno, &mut timer).await {
+            if !link_rx_up(linkno).await {
                return 0;
            }
            count += 1;
@ -480,7 +462,7 @@ pub mod drtio {
        aux_mutex: &Rc<Mutex<bool>>,
        routing_table: &RoutingTable,
        up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
-        mut timer: GlobalTimer,
+        timer: GlobalTimer,
    ) {
        let mut up_links = [false; csr::DRTIO.len()];
        loop {
@ -488,35 +470,16 @@ pub mod drtio {
                let linkno = linkno as u8;
                if up_links[linkno as usize] {
                    /* link was previously up */
-                    if link_rx_up(linkno, &mut timer).await {
+                    if link_rx_up(linkno).await {
                        process_unsolicited_aux(aux_mutex, linkno, routing_table).await;
                        process_local_errors(linkno).await;
                    } else {
                        info!("[LINK#{}] link is down", linkno);
                        up_links[linkno as usize] = false;
                        #[cfg(has_drtio_eem)]
                        if DRTIO_EEM_LINKNOS.contains(&(linkno as usize)) {
                            unsafe {
                                csr::eem_transceiver::rx_ready_write(0);
                            }
                            while !matches!(drtioaux_async::recv(linkno).await, Ok(None)) {}
                        }
                    }
                } else {
                    /* link was previously down */
-                    #[cfg(has_drtio_eem)]
+                    if link_rx_up(linkno).await {
                    if DRTIO_EEM_LINKNOS.contains(&(linkno as usize)) {
                        let eem_trx_no = linkno - DRTIO_EEM_LINKNOS.start as u8;
                        if !unsafe { drtio_eem::align_wordslip(&mut timer, eem_trx_no) } {
                            continue;
                        }
                        unsafe {
                            csr::eem_transceiver::rx_ready_write(1);
                        }
                    }
                    if link_rx_up(linkno, &mut timer).await {
                        info!("[LINK#{}] link RX became up, pinging", linkno);
                        let ping_count = ping_remote(aux_mutex, linkno, routing_table, timer).await;
                        if ping_count > 0 {
@ -560,7 +523,7 @@ pub mod drtio {
        for linkno in 0..csr::DRTIO.len() {
            let linkno = linkno as u8;
-            if task::block_on(link_rx_up(linkno, &mut timer)) {
+            if task::block_on(link_rx_up(linkno)) {
                let reply = task::block_on(aux_transact(
                    &aux_mutex,
                    linkno,
@ -577,7 +540,7 @@ pub mod drtio {
        }
    }
-    pub async fn partition_data<PacketF, HandlerF>(
+    async fn partition_data<PacketF, HandlerF>(
        linkno: u8,
        aux_mutex: &Rc<Mutex<bool>>,
        routing_table: &RoutingTable,
--- a/src/rustfmt.toml
+++ b/src/rustfmt.toml
@ -54,7 +54,7 @@ use_field_init_shorthand = false
 force_explicit_abi = true
 condense_wildcard_suffixes = false
 color = "Auto"
-required_version = "1.4.37"
+required_version = "1.4.32"
 unstable_features = false
 disable_all_formatting = false
 skip_children = false
@ -65,4 +65,4 @@ report_todo = "Never"
 report_fixme = "Never"
 ignore = []
 emit_mode = "Files"
-make_backup = false
+make_backup = false
--- a/src/satman/Cargo.toml.tpl
+++ b/src/satman/Cargo.toml.tpl
@ -15,9 +15,7 @@ build_zynq = { path = "../libbuild_zynq" }
 [dependencies]
 log = { version = "0.4", default-features = false }
-byteorder = { version = "1.3", default-features = false }
+core_io = { version = "0.1", features = ["collections"] }
 core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
 crc = { version = "1.7", default-features = false }
 cslice = "0.3"
 embedded-hal = "0.2"
--- a/src/satman/src/main.rs
+++ b/src/satman/src/main.rs
@ -1,12 +1,10 @@
 #![no_std]
 #![no_main]
-#![feature(alloc_error_handler, never_type, panic_info_message)]
+#![feature(alloc_error_handler, try_trait, never_type, panic_info_message)]
 #[macro_use]
 extern crate log;
 extern crate byteorder;
 extern crate core_io;
 extern crate crc;
 extern crate cslice;
 extern crate embedded_hal;
@ -40,18 +38,16 @@ use libboard_artiq::{drtio_routing, drtioaux,
                     pl::csr};
 #[cfg(feature = "target_kasli_soc")]
 use libboard_zynq::error_led::ErrorLED;
-use libboard_zynq::{i2c::I2c, print, println, slcr, time::Milliseconds, timer::GlobalTimer};
+use libboard_zynq::{i2c::I2c, print, println, time::Milliseconds, timer::GlobalTimer};
 use libconfig::Config;
 use libcortex_a9::{l2c::enable_l2_cache, regs::MPIDR};
 use libregister::RegisterR;
 use libsupport_zynq::{exception_vectors, ram};
 use mgmt::Manager as CoreManager;
 use routing::Router;
 use subkernel::Manager as KernelManager;
 mod analyzer;
 mod dma;
 mod mgmt;
 mod repeater;
 mod routing;
 mod subkernel;
@ -153,7 +149,6 @@ fn process_aux_packet(
    dma_manager: &mut DmaManager,
    analyzer: &mut Analyzer,
    kernel_manager: &mut KernelManager,
    core_manager: &mut CoreManager,
    router: &mut Router,
 ) -> Result<(), drtioaux::Error> {
    // In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
@ -1016,335 +1011,6 @@ fn process_aux_packet(
            }
            Ok(())
        }
        drtioaux::Packet::CoreMgmtGetLogRequest {
            destination: _destination,
            clear,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            let mut data_slice = [0; SAT_PAYLOAD_MAX_SIZE];
            let meta = core_manager.log_get_slice(&mut data_slice, clear);
            drtioaux::send(
                0,
                &drtioaux::Packet::CoreMgmtGetLogReply {
                    last: meta.status.is_last(),
                    length: meta.len as u16,
                    data: data_slice,
                },
            )
        }
        drtioaux::Packet::CoreMgmtClearLogRequest {
            destination: _destination,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            mgmt::clear_log();
            drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
        }
        drtioaux::Packet::CoreMgmtSetLogLevelRequest {
            destination: _destination,
            log_level,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            if let Ok(level_filter) = mgmt::byte_to_level_filter(log_level) {
                info!("Changing log level to {}", level_filter);
                log::set_max_level(level_filter);
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
            } else {
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
            }
        }
        drtioaux::Packet::CoreMgmtSetUartLogLevelRequest {
            destination: _destination,
            log_level,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            if let Ok(level_filter) = mgmt::byte_to_level_filter(log_level) {
                info!("Changing UART log level to {}", level_filter);
                unsafe {
                    logger::BufferLogger::get_logger()
                        .as_ref()
                        .unwrap()
                        .set_uart_log_level(level_filter);
                }
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
            } else {
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
            }
        }
        drtioaux::Packet::CoreMgmtConfigReadRequest {
            destination: _destination,
            length,
            key,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            let mut value_slice = [0; SAT_PAYLOAD_MAX_SIZE];
            let key_slice = &key[..length as usize];
            if !key_slice.is_ascii() {
                error!("invalid key");
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
            } else {
                let key = core::str::from_utf8(key_slice).unwrap();
                if core_manager.fetch_config_value(key).is_ok() {
                    let meta = core_manager.get_config_value_slice(&mut value_slice);
                    drtioaux::send(
                        0,
                        &drtioaux::Packet::CoreMgmtConfigReadReply {
                            last: meta.status.is_last(),
                            length: meta.len as u16,
                            value: value_slice,
                        },
                    )
                } else {
                    drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
                }
            }
        }
        drtioaux::Packet::CoreMgmtConfigReadContinue {
            destination: _destination,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            let mut value_slice = [0; SAT_PAYLOAD_MAX_SIZE];
            let meta = core_manager.get_config_value_slice(&mut value_slice);
            drtioaux::send(
                0,
                &drtioaux::Packet::CoreMgmtConfigReadReply {
                    last: meta.status.is_last(),
                    length: meta.len as u16,
                    value: value_slice,
                },
            )
        }
        drtioaux::Packet::CoreMgmtConfigWriteRequest {
            destination: _destination,
            last,
            length,
            data,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            core_manager.add_config_data(&data, length as usize);
            let mut succeeded = true;
            if last {
                succeeded = core_manager.write_config().is_ok();
                core_manager.clear_config_data();
            }
            drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded })
        }
        drtioaux::Packet::CoreMgmtConfigRemoveRequest {
            destination: _destination,
            length,
            key,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            let key_slice = &key[..length as usize];
            if !key_slice.is_ascii() {
                error!("invalid key");
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
            } else {
                let key = core::str::from_utf8(key_slice).unwrap();
                let succeeded = core_manager.remove_config(key).is_ok();
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded })
            }
        }
        drtioaux::Packet::CoreMgmtConfigEraseRequest {
            destination: _destination,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            error!("config erase not supported on zynq device");
            drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
        }
        drtioaux::Packet::CoreMgmtRebootRequest {
            destination: _destination,
        } => {
            info!("received reboot request");
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })?;
            info!("reboot imminent");
            slcr::reboot();
            unreachable!();
        }
        drtioaux::Packet::CoreMgmtAllocatorDebugRequest {
            destination: _destination,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            error!("debug allocator not supported on zynq device");
            drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
        }
        drtioaux::Packet::CoreMgmtFlashRequest {
            destination: _destination,
            payload_length,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            core_manager.allocate_image_buffer(payload_length as usize);
            drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
        }
        drtioaux::Packet::CoreMgmtFlashAddDataRequest {
            destination: _destination,
            last,
            length,
            data,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            core_manager.add_image_data(&data, length as usize);
            if last {
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtDropLink)
            } else {
                drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
            }
        }
        drtioaux::Packet::CoreMgmtDropLinkAck {
            destination: _destination,
        } => {
            forward!(
                router,
                _routing_table,
                _destination,
                *rank,
                *self_destination,
                _repeaters,
                &packet,
                timer
            );
            unsafe {
                csr::gt_drtio::txenable_write(0);
            }
            core_manager.write_image();
            info!("reboot imminent");
            slcr::reboot();
            Ok(())
        }
        p => {
            warn!("received unexpected aux packet: {:?}", p);
@ -1363,7 +1029,6 @@ fn process_aux_packets(
    dma_manager: &mut DmaManager,
    analyzer: &mut Analyzer,
    kernel_manager: &mut KernelManager,
    core_manager: &mut CoreManager,
    router: &mut Router,
 ) {
    let result = drtioaux::recv(0).and_then(|packet| {
@ -1379,7 +1044,6 @@ fn process_aux_packets(
                dma_manager,
                analyzer,
                kernel_manager,
                core_manager,
                router,
            )
        } else {
@ -1576,7 +1240,7 @@ pub extern "C" fn main_core0() -> i32 {
    #[cfg(has_si549)]
    si549::helper_setup(&mut timer, &SI549_SETTINGS).expect("cannot initialize helper Si549");
-    let mut cfg = match Config::new() {
+    let cfg = match Config::new() {
        Ok(cfg) => cfg,
        Err(err) => {
            warn!("config initialization failed: {}", err);
@ -1651,7 +1315,6 @@ pub extern "C" fn main_core0() -> i32 {
        let mut dma_manager = DmaManager::new();
        let mut analyzer = Analyzer::new();
        let mut kernel_manager = KernelManager::new(&mut control);
        let mut core_manager = CoreManager::new(&mut cfg);
        drtioaux::reset(0);
        drtiosat_reset(false);
@ -1669,7 +1332,6 @@ pub extern "C" fn main_core0() -> i32 {
                &mut dma_manager,
                &mut analyzer,
                &mut kernel_manager,
                &mut core_manager,
                &mut router,
            );
            #[allow(unused_mut)]
--- a/src/satman/src/mgmt.rs
+++ b/src/satman/src/mgmt.rs
@ -1,149 +0,0 @@
 use alloc::vec::Vec;
 use byteorder::{ByteOrder, NativeEndian};
 use crc::crc32;
 use io::{ProtoRead, ProtoWrite};
 use libboard_artiq::{drtioaux_proto::SAT_PAYLOAD_MAX_SIZE,
                     logger::{BufferLogger, LogBufferRef}};
 use libconfig::Config;
 use log::{debug, error, info, warn, LevelFilter};
 use crate::routing::{SliceMeta, Sliceable};
 type Result<T> = core::result::Result<T, ()>;
 pub fn byte_to_level_filter(level_byte: u8) -> Result<LevelFilter> {
    Ok(match level_byte {
        0 => LevelFilter::Off,
        1 => LevelFilter::Error,
        2 => LevelFilter::Warn,
        3 => LevelFilter::Info,
        4 => LevelFilter::Debug,
        5 => LevelFilter::Trace,
        lv => {
            error!("unknown log level: {}", lv);
            return Err(());
        }
    })
 }
 fn get_logger_buffer() -> LogBufferRef<'static> {
    let logger = unsafe { BufferLogger::get_logger().as_mut().unwrap() };
    loop {
        if let Some(buffer_ref) = logger.buffer() {
            return buffer_ref;
        }
    }
 }
 pub fn clear_log() {
    let mut buffer = get_logger_buffer();
    buffer.clear();
 }
 pub struct Manager<'a> {
    cfg: &'a mut Config,
    last_log: Sliceable,
    config_payload: Vec<u8>,
    last_value: Sliceable,
    image_payload: Vec<u8>,
 }
 impl<'a> Manager<'_> {
    pub fn new(cfg: &mut Config) -> Manager {
        Manager {
            cfg: cfg,
            last_log: Sliceable::new(0, Vec::new()),
            config_payload: Vec::new(),
            last_value: Sliceable::new(0, Vec::new()),
            image_payload: Vec::new(),
        }
    }
    pub fn log_get_slice(&mut self, data_slice: &mut [u8; SAT_PAYLOAD_MAX_SIZE], consume: bool) -> SliceMeta {
        // Populate buffer if depleted
        if self.last_log.at_end() {
            let mut buffer = get_logger_buffer();
            self.last_log.extend(buffer.extract().as_bytes());
            if consume {
                buffer.clear();
            }
        }
        self.last_log.get_slice_satellite(data_slice)
    }
    pub fn fetch_config_value(&mut self, key: &str) -> Result<()> {
        self.cfg
            .read(&key)
            .map(|value| {
                debug!("got value");
                self.last_value = Sliceable::new(0, value)
            })
            .map_err(|_| warn!("read error: no such key"))
    }
    pub fn get_config_value_slice(&mut self, data_slice: &mut [u8; SAT_PAYLOAD_MAX_SIZE]) -> SliceMeta {
        self.last_value.get_slice_satellite(data_slice)
    }
    pub fn add_config_data(&mut self, data: &[u8], data_len: usize) {
        self.config_payload.write_all(&data[..data_len]).unwrap();
    }
    pub fn clear_config_data(&mut self) {
        self.config_payload.clear();
    }
    pub fn write_config(&mut self) -> Result<()> {
        let mut payload = &self.config_payload[..];
        let key = payload.read_string().map_err(|_err| error!("error on reading key"))?;
        debug!("write key: {}", key);
        let value = payload.read_bytes().unwrap();
        self.cfg
            .write(&key, value)
            .map(|()| debug!("write success"))
            .map_err(|err| error!("failed to write: {:?}", err))
    }
    pub fn remove_config(&mut self, key: &str) -> Result<()> {
        debug!("erase key: {}", key);
        self.cfg
            .remove(&key)
            .map(|()| debug!("erase success"))
            .map_err(|err| warn!("failed to erase: {:?}", err))
    }
    pub fn allocate_image_buffer(&mut self, image_size: usize) {
        self.image_payload = Vec::with_capacity(image_size);
    }
    pub fn add_image_data(&mut self, data: &[u8], data_len: usize) {
        self.image_payload.extend(&data[..data_len]);
    }
    pub fn write_image(&self) {
        let mut image = self.image_payload.clone();
        let image_ref = &image[..];
        let bin_len = image.len() - 4;
        let (image_ref, expected_crc) = {
            let (image_ref, crc_slice) = image_ref.split_at(bin_len);
            (image_ref, NativeEndian::read_u32(crc_slice))
        };
        let actual_crc = crc32::checksum_ieee(image_ref);
        if actual_crc == expected_crc {
            info!("CRC passed. Writing boot image to SD card...");
            image.truncate(bin_len);
            self.cfg.write("boot", image).expect("failed to write boot image");
        } else {
            panic!(
                "CRC failed, images have not been written to flash.\n(actual {:08x}, expected {:08x})",
                actual_crc, expected_crc
            );
        }
    }
 }
--- a/src/satman/src/routing.rs
+++ b/src/satman/src/routing.rs
@ -4,7 +4,7 @@ use core::cmp::min;
 #[cfg(has_drtio_routing)]
 use libboard_artiq::pl::csr;
 use libboard_artiq::{drtio_routing, drtioaux,
-                     drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE, SAT_PAYLOAD_MAX_SIZE}};
+                     drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE}};
 pub struct SliceMeta {
    pub destination: u8,
@ -58,7 +58,6 @@ impl Sliceable {
    }
    get_slice_fn!(get_slice_master, MASTER_PAYLOAD_MAX_SIZE);
    get_slice_fn!(get_slice_satellite, SAT_PAYLOAD_MAX_SIZE);
 }
 // Packets from downstream (further satellites) are received and routed appropriately.
--- a/src/satman/src/subkernel.rs
+++ b/src/satman/src/subkernel.rs
@ -2,7 +2,7 @@ use alloc::{collections::BTreeMap,
            format,
            string::{String, ToString},
            vec::Vec};
-use core::{slice, str};
+use core::{option::NoneError, slice, str};
 use core_io::{Error as IoError, Write};
 use cslice::AsCSlice;
@ -65,6 +65,12 @@ pub enum Error {
    DmaError(DmaError),
 }
 impl From<NoneError> for Error {
    fn from(_: NoneError) -> Error {
        Error::KernelNotFound
    }
 }
 impl From<IoError> for Error {
    fn from(_value: IoError) -> Error {
        Error::SubkernelIoError
@ -310,7 +316,7 @@ impl<'a> Manager<'_> {
                            complete: false,
                        },
                    );
-                    self.kernels.get_mut(&id).ok_or_else(|| Error::KernelNotFound)?
+                    self.kernels.get_mut(&id)?
                } else {
                    kernel
                }
@ -323,7 +329,7 @@ impl<'a> Manager<'_> {
                        complete: false,
                    },
                );
-                self.kernels.get_mut(&id).ok_or_else(|| Error::KernelNotFound)?
+                self.kernels.get_mut(&id)?
            }
        };
        kernel.library.extend(&data[0..data_len]);
@ -390,19 +396,15 @@ impl<'a> Manager<'_> {
        if self.session.id == id && self.session.kernel_state == KernelState::Loaded {
            return Ok(());
        }
-        if !self.kernels.get(&id).ok_or_else(|| Error::KernelNotFound)?.complete {
+        if !self.kernels.get(&id)?.complete {
            return Err(Error::KernelNotFound);
        }
        self.session = Session::new(id);
        self.control.restart();
-        self.control.tx.send(kernel::Message::LoadRequest(
+        self.control
-            self.kernels
+            .tx
-                .get(&id)
+            .send(kernel::Message::LoadRequest(self.kernels.get(&id)?.library.clone()));
                .ok_or_else(|| Error::KernelNotFound)?
                .library
                .clone(),
        ));
        let reply = self.control.rx.recv();
        match reply {
            kernel::Message::LoadCompleted => Ok(()),
Author	SHA1	Message	Date
newell	463efcf194	Clean up warning take 2	2024-11-01 17:28:53 -07:00
newell	b3ab7a7950	Clean up comments and warning	2024-11-01 17:26:46 -07:00
newell	7bb74f83ee	Set fclk0 for ebaz4205	2024-11-01 17:22:05 -07:00