newell
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

Clean up comments and warning

This commit is contained in:
newell 2024-11-01 17:26:46 -07:00
parent 7bb74f83ee
commit b3ab7a7950
1 changed files with 1 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/runtime/src/rtio_clocking.rs
View File

@ -454,10 +454,7 @@ fn set_fclk0_freq(clk: RtioClock, cfg: &Config) {
.modify(|_, w| w.divisor0(divisor0).divisor1(divisor1));
});
} else {
warn!(
"Could not set fclk0 for target frequency of '{:?}' with available divisors",
target_freq
);
warn!("Could not set fclk0 for target frequency of '{:?}'", target_freq);
}
}
@ -489,7 +486,6 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
#[cfg(feature = "target_ebaz4205")]
{
// Set FPGA0_FCLK
match clk {
RtioClock::Int_100 | RtioClock::Int_125 | RtioClock::Int_150 => {
set_fclk0_freq(clk, cfg);