forked from M-Labs/artiq-zynq
Clean up comments and warning
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@ -454,10 +454,7 @@ fn set_fclk0_freq(clk: RtioClock, cfg: &Config) {
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.modify(|_, w| w.divisor0(divisor0).divisor1(divisor1));
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});
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} else {
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warn!(
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"Could not set fclk0 for target frequency of '{:?}' with available divisors",
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target_freq
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);
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warn!("Could not set fclk0 for target frequency of '{:?}'", target_freq);
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}
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}
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@ -489,7 +486,6 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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#[cfg(feature = "target_ebaz4205")]
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{
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// Set FPGA0_FCLK
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match clk {
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RtioClock::Int_100 | RtioClock::Int_125 | RtioClock::Int_150 => {
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set_fclk0_freq(clk, cfg);
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