artiq-zynq

Author	SHA1	Message	Date
linuswck	8fd1306145	zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL - Port from artiq repo - Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL - Add IDELAYCTRL for IDEALYE2 in EEM Serdes	2023-10-10 11:21:34 +08:00
mwojcik	46b2687d70	RTIO/SYS Clock merge Co-authored-by: mwojcik <mw@m-labs.hk> Co-committed-by: mwojcik <mw@m-labs.hk>	2023-02-17 15:52:43 +08:00

Author

SHA1

Message

Date

linuswck

8fd1306145

zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL

- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes

2023-10-10 11:21:34 +08:00

mwojcik

46b2687d70

RTIO/SYS Clock merge

Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>

2023-02-17 15:52:43 +08:00