Commit Graph

5 Commits (78bc1627495708f6011128d50b4af2998d02c37b)

Author SHA1 Message Date
mwojcik 78bc162749 rtio_clocking: remove loop 2022-04-12 13:33:52 +08:00
occheung 6c834899e9 si5324: fix clock source 2022-03-09 13:55:36 +08:00
spaqin 4f2a0986da rtio_clocking: fix wrong descriptions 2022-03-03 10:24:13 +08:00
mwojcik 31fb2b388a Support for DRTIO 100MHz (#155)
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-12-03 17:19:42 +08:00
mwojcik 8be5048cd3 upgrade to new clock configuration system (#152)
As mentioned in https://github.com/m-labs/artiq/issues/1735 - this is the Zynq version.

Reviewed-on: #152
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-11-29 11:17:59 +08:00