5cfcee6d20
satman: not a library - made closer to runtime
2021-09-01 11:05:46 +02:00
37e8b576b1
satellite:
...
* fixing repeaters that can't exist on zc706
* fixing various warnings
* fixed timer and i2c references
2021-08-31 15:25:56 +02:00
36bf30c446
satman: removed irrelevant (kasli v2) code
2021-08-31 13:47:43 +02:00
e56f99b3ae
satman: straightened up drtio interface
2021-08-31 12:46:52 +02:00
f80f2ac99d
added support for satellite variants in nix-build
2021-08-31 11:55:34 +02:00
db9b744825
satman: fixed timeout millisecond/u64 mismatch
2021-08-30 15:06:46 +02:00
be0baf5da8
satman: adjusted drtio::Error instances
2021-08-30 14:38:00 +02:00
59cf4bc689
libboard_zynq: fully modified to work with core_io
2021-08-27 15:16:13 +02:00
581f6c6b4e
libboard_artiq: tried moving drtio to io::proto
2021-08-27 14:44:54 +02:00
e0516eeda9
libio: removed custom read/write, moved to core_io
2021-08-27 13:12:19 +02:00
9b2b1dadaa
satman: repeater fixes, missing code
2021-08-26 15:20:33 +02:00
cb3f0a404c
libio: read/write traits from libio not core_io
2021-08-26 14:59:04 +02:00
10cbea72a2
clean up in dependencies
2021-08-26 13:16:51 +02:00
ff7ba56d26
forgot to remove a debug print
2021-08-26 12:54:19 +02:00
39d522e1a7
drtioaux_proto: removed failure, need to fix traits
2021-08-25 13:03:54 +02:00
a8a2da575b
libboard_artiq: added mem.rs, yet to fix drtioaux
2021-08-24 14:11:30 +02:00
37eb4669fb
makefile: satman support, separated from runtime
2021-08-24 13:57:10 +02:00
b585eaaa37
zc706: added memory iface generator
2021-08-24 13:51:38 +02:00
1358c8bfe9
zc706 gateware: base class for drtio is SoCCore
2021-08-24 12:01:04 +02:00
b2d9003d9f
drtioaucontroller: made two decoders
2021-08-20 15:13:56 +02:00
e43684a3ed
moved AXI SRAM to migen-axi
2021-08-18 12:36:17 +02:00
7b868e1c9d
few fixes, typos and missed unnecessary statements
2021-08-17 13:16:02 +02:00
61f81cec47
sram: redesigned write FSM. removed unused signals
2021-08-17 11:10:08 +02:00
3e1d14ff38
replaced increment logic with ready Incr module
2021-08-16 15:33:50 +02:00
67ed7fae78
sram: or operator in wrong place for wrapped burst
2021-08-16 12:05:23 +02:00
f015d6732b
sram: support for different burst settings on read
2021-08-16 11:51:50 +02:00
b6dd5bea68
sram: fixed wrong assumptions on some signals
2021-08-13 14:58:18 +02:00
bfe0c34f57
sram: rewrote read fsm for sram
2021-08-13 14:14:43 +02:00
39509f01d6
aux_controller: sram ported to axi, first attempt
2021-08-13 13:06:10 +02:00
066987bf07
aux_controller: started porting from wb to axi
2021-08-11 14:34:44 +02:00
7ff59f57a9
gateware: updated gtx interface
2021-08-10 15:11:21 +02:00
118893c0b2
disabled adding axi slave/mem
...
drtioauxcontroller uses AXI rather than Wishbone
still won't compile - unresolved clock domain error
2021-08-06 15:25:59 +02:00
ae86bbb76e
zc706 gateware fixes:
...
replaced crg cd_sys.clk with ps7.cd_sys.clk
restored gpio
removed mentions of i2c
user_sma_clock consumed by _RTIOCRG already
2021-08-06 13:31:16 +02:00
d68cf7dd49
gateware: replaced wb slave w/ axi (diff soccore)
2021-08-06 11:05:49 +02:00
f9860a61b7
sys_clk_freq is actually 125mhz
2021-08-06 10:39:37 +02:00
d1705113aa
kasli: gtx transcvr expects separate tx/rx pads
2021-08-06 10:05:45 +02:00
97dfa07bdb
determined probable sys_clk_freq for GTX transcvr
2021-08-06 10:05:04 +02:00
f45fa28dac
satman:
...
* added Zynq-specific impls of basic functions (main/panic/irq)
* added makefile definition
* fixed drtioaux compilation error (feature never_type)
2021-08-05 16:05:44 +02:00
ecc8a0ccc0
kasli-soc: qpll is not part of this board, removed mentions
2021-08-04 16:44:08 +02:00
e17b398483
added siphaser driver code for drtio satellites
2021-08-04 12:55:03 +02:00
b95692548e
Merge branch 'master' into drtio_port
2021-08-04 09:38:08 +02:00
18e05c91e1
zc706: si5324 is not needed for standalone target
2021-08-04 09:14:19 +08:00
e3d3cb2311
si5324: bring on par with mainline ARTIQ ( #132 )
...
si5324 driver in runtime should be now equal in function to the one in artiq.
kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.
Reviewed-on: #132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-08-04 09:12:38 +08:00
98b3b74bc2
added kasli-soc variants based on demo
2021-08-03 11:54:44 +02:00
6a9729bede
Merge branch 'master' into drtio_port
2021-08-03 09:56:14 +02:00
b2dd68bd92
removed unnecessary and wrong add_drtio
2021-08-03 09:52:50 +02:00
f543501012
si5324: remove debug print
2021-08-02 14:14:59 +08:00
cafbe97e47
zc706: added targets to default.nix, fixed wrong base cls
2021-07-30 15:14:40 +02:00
3ba7fe1e6b
kasli_soc uses gtx transceiver instead of gtp
2021-07-30 12:52:58 +02:00
111ac0c716
runtime: clock Si5324 from its crystal
2021-07-30 17:07:58 +08:00
