 linuswck
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e6372b9766
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zynq_clocking: Allow ext signal to set cur_clk csr
- for example, current_clock csr can be connected to tx_init.done
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2023-11-07 18:55:08 +08:00 |
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linuswck
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07044752b6
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zynq_clocking: add ext_async_rst to AsyncRstSYNCR
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2023-11-07 18:55:08 +08:00 |
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linuswck
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79fc5a7789
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zynq_clocking: expose mmcm_locked for SYSCRG
- mmcm_locked -> self.mmcm_locked
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2023-11-07 18:55:08 +08:00 |
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linuswck
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8fd1306145
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zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL
- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
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2023-10-10 11:21:34 +08:00 |
 mwojcik
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46b2687d70
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RTIO/SYS Clock merge
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
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2023-02-17 15:52:43 +08:00 |