M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

zc706 gateware: fix rust_cfg lacking has_si5324

Browse Source
This commit is contained in:
mwojcik 2021-08-02 15:06:29 +02:00
parent f70ce89ee6
commit e3e51b5ab1
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gateware/zc706.py
View File

@ -82,7 +82,7 @@ class ZC706(SoCCore):
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
self.config["HAS_SI5324"] = None
self.rustc_cfg["HAS_SI5324"] = None
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")