From e3e51b5ab127bb2fa5b05839a7365bf55edaf450 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 2 Aug 2021 15:06:29 +0200 Subject: [PATCH] zc706 gateware: fix rust_cfg lacking has_si5324 --- src/gateware/zc706.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index f5005b9..071fa94 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -82,7 +82,7 @@ class ZC706(SoCCore): platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - self.config["HAS_SI5324"] = None + self.rustc_cfg["HAS_SI5324"] = None self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n")