diff --git a/src/gateware/test_dma.py b/src/gateware/test_dma.py
index c0786a3..456205f 100644
--- a/src/gateware/test_dma.py
+++ b/src/gateware/test_dma.py
@@ -168,7 +168,7 @@ class FullStackTB(Module):
         bus = axi.Interface(ws*8)
         self.memory = AXIMemorySim(bus, sequence)
         self.submodules.dut = dma.DMA(bus)
-        self.submodules.tsc = rtio.TSC("async")
+        self.submodules.tsc = rtio.TSC()
         self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
         self.comb += self.dut.cri.connect(self.rtio.cri)